1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #include <arch/romstage.h> 4 #include <cbmem.h> 5 #include <assert.h> 6 #include <cpu/x86/mtrr.h> 7 #include <cpu/x86/smm.h> 8 #include <device/device.h> 9 #include <device/pci_def.h> 10 #include <device/pci_ops.h> 11 #include <soc/pci_devs.h> 12 #include <soc/systemagent.h> 13 14 /* Returns base of requested region encoded in the system agent. */ system_agent_region_base(size_t reg)15static inline uintptr_t system_agent_region_base(size_t reg) 16 { 17 #if defined(__SIMPLE_DEVICE__) 18 pci_devfn_t dev = SA_DEV_ROOT; 19 #else 20 struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); 21 #endif 22 /* All regions concerned for have 1 MiB alignment. */ 23 return ALIGN_DOWN(pci_read_config32(dev, reg), 1 * MiB); 24 } 25 smm_region_start(void)26static inline uintptr_t smm_region_start(void) 27 { 28 return system_agent_region_base(TSEGMB); 29 } 30 smm_region_size(void)31static inline size_t smm_region_size(void) 32 { 33 return system_agent_region_base(TOLUD) - smm_region_start(); 34 } 35 smm_region(uintptr_t * start,size_t * size)36void smm_region(uintptr_t *start, size_t *size) 37 { 38 *start = smm_region_start(); 39 *size = smm_region_size(); 40 } 41 fill_postcar_frame(struct postcar_frame * pcf)42void fill_postcar_frame(struct postcar_frame *pcf) 43 { 44 /* 45 * We need to make sure ramstage will be run cached. At this point exact 46 * location of ramstage in cbmem is not known. Instruct postcar to cache 47 * 16 megs under cbmem top which is a safe bet to cover ramstage. 48 */ 49 const uintptr_t top_of_ram = cbmem_top(); 50 postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, 51 MTRR_TYPE_WRBACK); 52 53 /* Cache the TSEG region */ 54 postcar_enable_tseg_cache(pcf); 55 } 56