1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <device/device.h> 4 #include <device/pci.h> 5 #include <console/console.h> 6 #include <arch/io.h> 7 #include <cpu/x86/smm.h> 8 #include <cpu/intel/smm_reloc.h> 9 10 #include <soc/iomap.h> 11 #include <soc/soc_util.h> 12 #include <soc/pm.h> 13 #include <soc/smm.h> 14 smm_southbridge_clear_state(void)15void smm_southbridge_clear_state(void) 16 { 17 uint32_t smi_en; 18 19 smi_en = inl((uint16_t)(get_pmbase() + SMI_EN)); 20 if (smi_en & APMC_EN) { 21 printk(BIOS_INFO, "SMI# handler already enabled?\n"); 22 return; 23 } 24 25 /* Dump and clear status registers */ 26 clear_smi_status(); 27 clear_pm1_status(); 28 clear_tco_status(); 29 clear_gpe_status(); 30 clear_pmc_status(); 31 } 32 smm_southbridge_enable(uint16_t pm1_events)33static void smm_southbridge_enable(uint16_t pm1_events) 34 { 35 printk(BIOS_DEBUG, "Enabling SMIs.\n"); 36 /* Configure events Disable PCIe wake. */ 37 enable_pm1(pm1_events | PCIEXPWAK_DIS); 38 disable_gpe(PME_B0_EN); 39 40 /* Enable SMI generation: 41 * - on APMC writes (io 0xb2) 42 * - on writes to SLP_EN (sleep states) 43 * - on writes to GBL_RLS (bios commands) 44 * No SMIs: 45 * - on TCO events 46 * - on microcontroller writes (io 0x62/0x66) 47 */ 48 enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); 49 } 50 global_smi_enable(void)51void global_smi_enable(void) 52 { 53 smm_southbridge_enable(PWRBTN_EN | GBL_EN); 54 } 55