1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <acpi/acpi.h>
4 #include <acpi/acpi_gnvs.h>
5 #include <acpi/acpigen.h>
6 #include <arch/ioapic.h>
7 #include <arch/smp/mpspec.h>
8 #include <console/console.h>
9 #include <device/device.h>
10 #include <device/mmio.h>
11 #include <device/pci_ops.h>
12 #include <intelblocks/acpi.h>
13 #include <intelblocks/cpulib.h>
14 #include <intelblocks/pmclib.h>
15 #include <soc/cpu.h>
16 #include <soc/iomap.h>
17 #include <soc/nvs.h>
18 #include <soc/pci_devs.h>
19 #include <soc/pm.h>
20 #include <soc/soc_chip.h>
21 #include <soc/systemagent.h>
22
23 /*
24 * List of supported C-states in this processor.
25 */
26 enum {
27 C_STATE_C0, /* 0 */
28 C_STATE_C1, /* 1 */
29 C_STATE_C1E, /* 2 */
30 C_STATE_C6_SHORT_LAT, /* 3 */
31 C_STATE_C6_LONG_LAT, /* 4 */
32 C_STATE_C7_SHORT_LAT, /* 5 */
33 C_STATE_C7_LONG_LAT, /* 6 */
34 C_STATE_C7S_SHORT_LAT, /* 7 */
35 C_STATE_C7S_LONG_LAT, /* 8 */
36 C_STATE_C8, /* 9 */
37 C_STATE_C9, /* 10 */
38 C_STATE_C10, /* 11 */
39 NUM_C_STATES
40 };
41
42 static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
43 [C_STATE_C0] = {},
44 [C_STATE_C1] = {
45 .latency = C1_LATENCY,
46 .power = C1_POWER,
47 .resource = MWAIT_RES(0, 0),
48 },
49 [C_STATE_C1E] = {
50 .latency = C1_LATENCY,
51 .power = C1_POWER,
52 .resource = MWAIT_RES(0, 1),
53 },
54 [C_STATE_C6_SHORT_LAT] = {
55 .latency = C6_LATENCY,
56 .power = C6_POWER,
57 .resource = MWAIT_RES(2, 0),
58 },
59 [C_STATE_C6_LONG_LAT] = {
60 .latency = C6_LATENCY,
61 .power = C6_POWER,
62 .resource = MWAIT_RES(2, 1),
63 },
64 [C_STATE_C7_SHORT_LAT] = {
65 .latency = C7_LATENCY,
66 .power = C7_POWER,
67 .resource = MWAIT_RES(3, 0),
68 },
69 [C_STATE_C7_LONG_LAT] = {
70 .latency = C7_LATENCY,
71 .power = C7_POWER,
72 .resource = MWAIT_RES(3, 1),
73 },
74 [C_STATE_C7S_SHORT_LAT] = {
75 .latency = C7_LATENCY,
76 .power = C7_POWER,
77 .resource = MWAIT_RES(3, 2),
78 },
79 [C_STATE_C7S_LONG_LAT] = {
80 .latency = C7_LATENCY,
81 .power = C7_POWER,
82 .resource = MWAIT_RES(3, 3),
83 },
84 [C_STATE_C8] = {
85 .latency = C8_LATENCY,
86 .power = C8_POWER,
87 .resource = MWAIT_RES(4, 0),
88 },
89 [C_STATE_C9] = {
90 .latency = C9_LATENCY,
91 .power = C9_POWER,
92 .resource = MWAIT_RES(5, 0),
93 },
94 [C_STATE_C10] = {
95 .latency = C10_LATENCY,
96 .power = C10_POWER,
97 .resource = MWAIT_RES(6, 0),
98 },
99 };
100
101 static int cstate_set_non_s0ix[] = {
102 C_STATE_C1,
103 C_STATE_C6_LONG_LAT,
104 C_STATE_C7S_LONG_LAT
105 };
106
107 static int cstate_set_s0ix[] = {
108 C_STATE_C1,
109 C_STATE_C7S_LONG_LAT,
110 C_STATE_C10
111 };
112
soc_get_cstate_map(size_t * entries)113 const acpi_cstate_t *soc_get_cstate_map(size_t *entries)
114 {
115 static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix),
116 ARRAY_SIZE(cstate_set_non_s0ix))];
117 int *set;
118 int i;
119
120 config_t *config = config_of_soc();
121
122 int is_s0ix_enable = config->s0ix_enable;
123
124 if (is_s0ix_enable) {
125 *entries = ARRAY_SIZE(cstate_set_s0ix);
126 set = cstate_set_s0ix;
127 } else {
128 *entries = ARRAY_SIZE(cstate_set_non_s0ix);
129 set = cstate_set_non_s0ix;
130 }
131
132 for (i = 0; i < *entries; i++) {
133 map[i] = cstate_map[set[i]];
134 map[i].ctype = i + 1;
135 }
136 return map;
137 }
138
soc_power_states_generation(int core_id,int cores_per_package)139 void soc_power_states_generation(int core_id, int cores_per_package)
140 {
141 config_t *config = config_of_soc();
142
143 if (config->eist_enable)
144 /* Generate P-state tables */
145 generate_p_state_entries(core_id, cores_per_package);
146 }
147
soc_fill_fadt(acpi_fadt_t * fadt)148 void soc_fill_fadt(acpi_fadt_t *fadt)
149 {
150 const uint16_t pmbase = ACPI_BASE_ADDRESS;
151
152 config_t *config = config_of_soc();
153
154 fadt->pm_tmr_blk = pmbase + PM1_TMR;
155 fadt->pm_tmr_len = 4;
156
157 fill_fadt_extended_pm_io(fadt);
158
159 fadt->preferred_pm_profile = PM_MOBILE;
160
161 if (config->s0ix_enable)
162 fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
163 }
164
soc_read_sci_irq_select(void)165 uint32_t soc_read_sci_irq_select(void)
166 {
167 return read32p(soc_read_pmc_base() + IRQ_REG);
168 }
169
soc_fill_dmar(unsigned long current)170 static unsigned long soc_fill_dmar(unsigned long current)
171 {
172 uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
173 bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
174
175 if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) {
176 unsigned long tmp = current;
177
178 current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar);
179 current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
180
181 acpi_dmar_drhd_fixup(tmp, current);
182 }
183
184 uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK;
185 bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED;
186
187 if (vtvc0bar && vtvc0en) {
188 const unsigned long tmp = current;
189
190 current += acpi_create_dmar_drhd_4k(current,
191 DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
192 current += acpi_create_dmar_ds_ioapic_from_hw(current,
193 IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV,
194 V_P2SB_CFG_IBDF_FUNC);
195 current += acpi_create_dmar_ds_msi_hpet(current,
196 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV,
197 V_P2SB_CFG_HBDF_FUNC);
198
199 acpi_dmar_drhd_fixup(tmp, current);
200 }
201
202 /* Add RMRR entry */
203 const unsigned long tmp = current;
204 current += acpi_create_dmar_rmrr(current, 0,
205 sa_get_gsm_base(), sa_get_tolud_base() - 1);
206 current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
207 acpi_dmar_rmrr_fixup(tmp, current);
208
209 return current;
210 }
211
sa_write_acpi_tables(const struct device * dev,unsigned long current,struct acpi_rsdp * rsdp)212 unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current,
213 struct acpi_rsdp *rsdp)
214 {
215 acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
216
217 /*
218 * Create DMAR table only if we have VT-d capability and FSP does not override its
219 * feature.
220 */
221 if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) ||
222 !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED))
223 return current;
224
225 printk(BIOS_DEBUG, "ACPI: * DMAR\n");
226 acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar);
227 current += dmar->header.length;
228 current = acpi_align_current(current);
229 acpi_add_table(rsdp, dmar);
230
231 return current;
232 }
233
soc_fill_gnvs(struct global_nvs * gnvs)234 void soc_fill_gnvs(struct global_nvs *gnvs)
235 {
236 config_t *config = config_of_soc();
237
238 /* Enable DPTF based on mainboard configuration */
239 gnvs->dpte = config->dptf_enable;
240
241 /* Set USB2/USB3 wake enable bitmaps. */
242 gnvs->u2we = config->usb2_wake_enable_bitmap;
243 gnvs->u3we = config->usb3_wake_enable_bitmap;
244 }
245
soc_madt_sci_irq_polarity(int sci)246 int soc_madt_sci_irq_polarity(int sci)
247 {
248 return MP_IRQ_POLARITY_HIGH;
249 }
250