1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _SOC_CHIP_H_ 4 #define _SOC_CHIP_H_ 5 6 #include <drivers/i2c/designware/dw_i2c.h> 7 #include <gpio.h> 8 #include <intelblocks/cfg.h> 9 #include <intelblocks/gspi.h> 10 #include <intelblocks/pcie_rp.h> 11 #include <intelblocks/power_limit.h> 12 #include <soc/gpe.h> 13 #include <soc/pch.h> 14 #include <soc/pci_devs.h> 15 #include <soc/pmc.h> 16 #include <soc/serialio.h> 17 #include <soc/usb.h> 18 #include <types.h> 19 20 #define MAX_HD_AUDIO_SDI_LINKS 2 21 #define MAX_HD_AUDIO_DMIC_LINKS 2 22 #define MAX_HD_AUDIO_SNDW_LINKS 4 23 #define MAX_HD_AUDIO_SSP_LINKS 6 24 #define MAX_PSE_TSN_PORTS 2 25 26 /* Define config parameters for In-Band ECC (IBECC). */ 27 #define MAX_IBECC_REGIONS 8 28 29 enum ibecc_mode { 30 IBECC_PER_REGION, 31 IBECC_NONE, 32 IBECC_ALL 33 }; 34 35 struct ehl_ibecc_config { 36 bool enable; 37 bool parity_en; 38 enum ibecc_mode mode; 39 bool region_enable[MAX_IBECC_REGIONS]; 40 uint16_t region_base[MAX_IBECC_REGIONS]; 41 uint16_t region_mask[MAX_IBECC_REGIONS]; 42 }; 43 44 /* TSN GBE Link Speed: 0: 2.5Gbps, 1: 1Gbps */ 45 enum tsn_gbe_link_speed { 46 Tsn_2_5_Gbps, 47 Tsn_1_Gbps, 48 }; 49 50 /* TSN Phy Interface Type: 1: RGMII, 2: SGMII, 3:SGMII+ */ 51 enum tsn_phy_type { 52 RGMII = 1, 53 SGMII = 2, 54 SGMII_plus = 3, 55 }; 56 57 /* TSN GBE PHY-to-MAC IRQ polarity: 0: falling edge, 1: rising edge */ 58 enum tsn_phy_irq_polarity { 59 FALLING_EDGE, 60 RISING_EDGE, 61 }; 62 63 /* 64 * PSE native pins and ownership assignment:- 65 * 0: Disable/pins are not owned by PSE/host 66 * 1: Pins are muxed to PSE IP, the IO is owned by PSE 67 * 2: Pins are muxed to PSE IP, the IO is owned by host 68 */ 69 enum pse_device_ownership { 70 Device_Disabled, 71 PSE_Owned, 72 Host_Owned, 73 }; 74 75 /* 76 * Enable external V1P05 Rail in: BIT0:S0i1/S0i2, 77 * BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5 78 * However, EHL does not support S0i1 and S0i2, 79 * hence removed the option. 80 */ 81 enum fivr_states { 82 FIVR_ENABLE_S0i3 = BIT(1), 83 FIVR_ENABLE_S3 = BIT(2), 84 FIVR_ENABLE_S4 = BIT(3), 85 FIVR_ENABLE_S5 = BIT(4), 86 FIVR_ENABLE_S3_S4_S5 = FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5, 87 FIVR_ENABLE_ALL_SX = FIVR_ENABLE_S0i3 | FIVR_ENABLE_S3_S4_S5, 88 }; 89 90 /* 91 * Enable the following for external V1p05 rail 92 * BIT1: Normal active voltage supported 93 * BIT2: Minimum active voltage supported 94 * BIT3: Minimum retention voltage supported 95 */ 96 enum fivr_supported_voltage { 97 FIVR_VOLTAGE_NORMAL = BIT(1), 98 FIVR_VOLTAGE_MIN_ACTIVE = BIT(2), 99 FIVR_VOLTAGE_MIN_RETENTION = BIT(3), 100 FIVR_ENABLE_ALL_VOLTAGE = FIVR_VOLTAGE_NORMAL | FIVR_VOLTAGE_MIN_ACTIVE | 101 FIVR_VOLTAGE_MIN_RETENTION, 102 }; 103 104 /* SATA speed limit */ 105 enum sata_speed_limit { 106 SATA_DEFAULT = 0, 107 SATA_GEN1, 108 SATA_GEN2 109 }; 110 111 struct soc_intel_elkhartlake_config { 112 /* Common struct containing soc config data required by common code */ 113 struct soc_intel_common_config common_soc_config; 114 115 /* Common struct containing power limits configuration information */ 116 struct soc_power_limits_config power_limits_config; 117 118 /* Gpio group routed to each dword of the GPE0 block. Values are 119 * of the form PMC_GPP_[A:U] or GPD. */ 120 uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ 121 uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */ 122 uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */ 123 124 /* Generic IO decode ranges */ 125 uint32_t gen1_dec; 126 uint32_t gen2_dec; 127 uint32_t gen3_dec; 128 uint32_t gen4_dec; 129 130 /* Enable S0iX support */ 131 int s0ix_enable; 132 /* Enable DPTF support */ 133 int dptf_enable; 134 135 /* Deep SX enable for both AC and DC */ 136 int deep_s3_enable_ac; 137 int deep_s3_enable_dc; 138 int deep_s5_enable_ac; 139 int deep_s5_enable_dc; 140 141 /* Deep Sx Configuration 142 * DSX_EN_WAKE_PIN - Enable WAKE# pin 143 * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin 144 * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */ 145 uint32_t deep_sx_config; 146 147 /* TCC activation offset */ 148 uint32_t tcc_offset; 149 uint32_t tcc_offset_clamp; 150 151 /* Memory Thermal Throttling: Enable - Default (0) / Disable (1) */ 152 bool MemoryThermalThrottlingDisable; 153 154 /* In-Band ECC (IBECC) configuration */ 155 struct ehl_ibecc_config ibecc; 156 157 /* FuSa (Functional Safety): Disable - Default (0) / Enable (1) */ 158 bool FuSaEnable; 159 160 /* System Agent dynamic frequency support. 161 * When enabled memory will be trained at different frequencies. 162 * 0:Disabled, 1:FixedPoint0(low), 2:FixedPoint1(mid), 3:FixedPoint2 163 * (high), 4:Enabled */ 164 enum { 165 SaGv_Disabled, 166 SaGv_FixedPoint0, 167 SaGv_FixedPoint1, 168 SaGv_FixedPoint2, 169 SaGv_Enabled, 170 } SaGv; 171 172 /* Rank Margin Tool. 1:Enable, 0:Disable */ 173 uint8_t RMT; 174 175 /* USB related */ 176 struct usb2_port_config usb2_ports[10]; 177 struct usb3_port_config usb3_ports[4]; 178 /* Wake Enable Bitmap for USB2 ports */ 179 uint16_t usb2_wake_enable_bitmap; 180 /* Wake Enable Bitmap for USB3 ports */ 181 uint16_t usb3_wake_enable_bitmap; 182 183 /* SATA related */ 184 uint8_t SataMode; 185 uint8_t SataSalpSupport; 186 uint8_t SataPortsEnable[CONFIG_MAX_SATA_PORTS]; 187 uint8_t SataPortsDevSlp[CONFIG_MAX_SATA_PORTS]; 188 uint8_t SataPortsSSD[CONFIG_MAX_SATA_PORTS]; 189 enum sata_speed_limit SataSpeed; 190 /* 191 * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. 192 * Default 0. Setting this to 1 disables the SATA Power Optimizer. 193 */ 194 uint8_t SataPwrOptimizeDisable; 195 /* 196 * SATA Port Enable Dito Config. 197 * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). 198 */ 199 uint8_t SataPortsEnableDitoConfig[CONFIG_MAX_SATA_PORTS]; 200 /* SataPortsDmVal is the DITO multiplier. Default is 15. */ 201 uint8_t SataPortsDmVal[CONFIG_MAX_SATA_PORTS]; 202 /* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */ 203 uint16_t SataPortsDitoVal[CONFIG_MAX_SATA_PORTS]; 204 205 /* Audio related */ 206 uint8_t PchHdaDspEnable; 207 uint8_t PchHdaAudioLinkHdaEnable; 208 uint8_t PchHdaSdiEnable[MAX_HD_AUDIO_SDI_LINKS]; 209 uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; 210 uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; 211 uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]; 212 213 /* PCIe Root Ports */ 214 uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; 215 216 /* PCIe output clocks type to PCIe devices. 217 * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, 218 * 0xFF: not used */ 219 uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC]; 220 221 /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to 222 * clksrc. */ 223 uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC]; 224 225 /* Enable PCIe Precision Time Measurement for Root Ports (disabled by default) */ 226 uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS]; 227 228 /* Probe CLKREQ# signal before enabling CLKREQ# based power management. 229 * Enable - Default (0) / Disable (1) */ 230 uint8_t PcieRpClkReqDetectDisable[CONFIG_MAX_ROOT_PORTS]; 231 232 /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ 233 uint8_t PcieRpAdvancedErrorReportingDisable[CONFIG_MAX_ROOT_PORTS]; 234 235 /* PCIe LTR: Enable - Default (0) / Disable (1) */ 236 uint8_t PcieRpLtrDisable[CONFIG_MAX_ROOT_PORTS]; 237 238 /* PCIe RP L1 substate */ 239 enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; 240 241 /* PCIe root port maximum payload size, default is set to 128 bytes. */ 242 enum { 243 RpMaxPayload_128, 244 RpMaxPayload_256, 245 } PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS]; 246 247 /* PCIe root port speed. 0: Auto (Default); 1: Gen1; 2: Gen2; 3: Gen3 */ 248 uint8_t PcieRpPcieSpeed[CONFIG_MAX_ROOT_PORTS]; 249 250 /* eMMC and SD */ 251 uint8_t ScsEmmcHs400Enabled; 252 uint8_t ScsEmmcDdr50Enabled; 253 254 /* Enable if SD Card Power Enable Signal is Active High */ 255 uint8_t SdCardPowerEnableActiveHigh; 256 257 /* HECI related */ 258 uint8_t Heci2Enable; 259 uint8_t Heci3Enable; 260 261 /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ 262 uint8_t eist_enable; 263 264 /* 265 * SerialIO device mode selection: 266 * PchSerialIoDisabled, 267 * PchSerialIoPci, 268 * PchSerialIoHidden, 269 * PchSerialIoLegacyUart, 270 * PchSerialIoSkipInit 271 */ 272 uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; 273 uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; 274 uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; 275 /* 276 * UARTn Default DMA/PIO Mode Enable(1)/Disable(0): 277 */ 278 uint8_t SerialIoUartDmaEnable[CONFIG_SOC_INTEL_UART_DEV_MAX]; 279 /* 280 * GSPIn Default Chip Enable(1)/Disable(0): 281 */ 282 uint8_t SerialIoGSpiCsEnable[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; 283 /* 284 * GSPIn Default Chip Select Mode: 285 * 0:Hardware Mode, 286 * 1:Software Mode 287 */ 288 uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; 289 /* 290 * GSPIn Default Chip Select State: 291 * 0: Low, 292 * 1: High 293 */ 294 uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; 295 /* 296 * SerialIo I2C Pads Termination Config: 297 * 0x0:Hardware default, 298 * 0x1:None, 299 * 0x13:1kOhm weak pull-up, 300 * 0x15:5kOhm weak pull-up, 301 * 0x19:20kOhm weak pull-up 302 */ 303 uint8_t SerialIoI2cPadsTermination[CONFIG_SOC_INTEL_I2C_DEV_MAX]; 304 305 /* 306 * TraceHubMode config 307 * 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode 308 */ 309 uint8_t TraceHubMode; 310 311 /* Debug interface selection */ 312 enum { 313 DEBUG_INTERFACE_RAM = (1 << 0), 314 DEBUG_INTERFACE_UART_8250IO = (1 << 1), 315 DEBUG_INTERFACE_USB3 = (1 << 3), 316 DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4), 317 DEBUG_INTERFACE_TRACEHUB = (1 << 5), 318 } debug_interface_flag; 319 320 /* GPIO SD card detect pin */ 321 unsigned int sdcard_cd_gpio; 322 323 /* 324 * Override GPIO PM configuration: 325 * 0: Use FSP default GPIO PM program, 326 * 1: coreboot to override GPIO PM program 327 */ 328 uint8_t gpio_override_pm; 329 330 /* 331 * GPIO PM configuration: 0 to disable, 1 to enable power gating 332 * Bit 6-7: Reserved 333 * Bit 5: MISCCFG_GPSIDEDPCGEN 334 * Bit 4: MISCCFG_GPRCOMPCDLCGEN 335 * Bit 3: MISCCFG_GPRTCDLCGEN 336 * Bit 2: MISCCFG_GSXLCGEN 337 * Bit 1: MISCCFG_GPDPCGEN 338 * Bit 0: MISCCFG_GPDLCGEN 339 */ 340 uint8_t gpio_pm[TOTAL_GPIO_COMM]; 341 342 /* DP config */ 343 /* 344 * Port config 345 * 0:Disabled, 1:eDP, 2:MIPI DSI 346 */ 347 uint8_t DdiPortAConfig; 348 uint8_t DdiPortBConfig; 349 uint8_t DdiPortCConfig; 350 351 /* Enable(1)/Disable(0) HPD */ 352 uint8_t DdiPortAHpd; 353 uint8_t DdiPortBHpd; 354 uint8_t DdiPortCHpd; 355 uint8_t DdiPort1Hpd; 356 uint8_t DdiPort2Hpd; 357 uint8_t DdiPort3Hpd; 358 uint8_t DdiPort4Hpd; 359 360 /* Enable(1)/Disable(0) DDC */ 361 uint8_t DdiPortADdc; 362 uint8_t DdiPortBDdc; 363 uint8_t DdiPortCDdc; 364 uint8_t DdiPort1Ddc; 365 uint8_t DdiPort2Ddc; 366 uint8_t DdiPort3Ddc; 367 uint8_t DdiPort4Ddc; 368 369 /* Skip CPU replacement check 370 * 0: disable 371 * 1: enable 372 * Setting this option to skip CPU replacement check to avoid the forced MRC training 373 * for the platforms with soldered down SOC. 374 */ 375 uint8_t SkipCpuReplacementCheck; 376 377 struct { 378 bool fivr_config_en; 379 enum fivr_states v1p05_state; 380 enum fivr_states vnn_state; 381 enum fivr_states vnn_sx_state; 382 enum fivr_supported_voltage v1p05_rail; 383 enum fivr_supported_voltage vnn_rail; 384 /* Icc max for V1p05 rail in mA */ 385 unsigned int v1p05_icc_max_ma; 386 /* Vnn voltage in mV */ 387 unsigned int vnn_sx_mv; 388 /* Transition time in microseconds: */ 389 /* From low current mode voltage to high current mode voltage */ 390 unsigned int vcc_low_high_us; 391 /* From retention mode voltage to high current mode voltage */ 392 unsigned int vcc_ret_high_us; 393 /* From retention mode voltage to low current mode voltage */ 394 unsigned int vcc_ret_low_us; 395 /* From off(0V) to high current mode voltage */ 396 unsigned int vcc_off_high_us; 397 /* RFI spread spectrum, in 0.1% increment. Range: 0.0% to 10.0% (0-100). */ 398 unsigned int spread_spectrum; 399 } fivr; 400 401 /* 402 * PCH power button override period. 403 * Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s 404 */ 405 u8 PchPmPwrBtnOverridePeriod; 406 407 /* GBE related (PCH & PSE) */ 408 /* TSN GBE Link Speed: 0: 2.5Gbps, 1: 1Gbps */ 409 enum tsn_gbe_link_speed PchTsnGbeLinkSpeed; 410 enum tsn_gbe_link_speed PseTsnGbeLinkSpeed[MAX_PSE_TSN_PORTS]; 411 /* TSN GBE SGMII Support: Disable (0) / Enable (1) */ 412 bool PchTsnGbeSgmiiEnable; 413 bool PseTsnGbeSgmiiEnable[MAX_PSE_TSN_PORTS]; 414 /* TSN GBE Multiple Virtual Channel: Disable (0) / Enable (1) */ 415 bool PchTsnGbeMultiVcEnable; 416 bool PseTsnGbeMultiVcEnable[MAX_PSE_TSN_PORTS]; 417 /* PSE TSN Phy Interface Type */ 418 enum tsn_phy_type PseTsnGbePhyType[MAX_PSE_TSN_PORTS]; 419 enum tsn_phy_irq_polarity pch_tsn_phy_irq_edge; 420 enum tsn_phy_irq_polarity pse_tsn_phy_irq_edge[MAX_PSE_TSN_PORTS]; 421 422 /* PSE related */ 423 /* 424 * PSE (Intel Programmable Services Engine) native pins and ownership 425 * assignment. If the device is configured as 'PSE owned', PSE will have 426 * full control of specific device and it will be hidden from coreboot 427 * and OS. If the device is configured as 'Host owned', the device will 428 * be visible to coreboot and OS as a PCI device, while PSE will still 429 * do some IP initialization and pin assignment works. 430 * 431 * PSE is still required during runtime to ensure any of PSE devices 432 * works properly. 433 */ 434 enum pse_device_ownership PseDmaOwn[3]; 435 enum pse_device_ownership PseUartOwn[6]; 436 enum pse_device_ownership PseHsuartOwn[4]; 437 enum pse_device_ownership PseQepOwn[4]; 438 enum pse_device_ownership PseI2cOwn[8]; 439 enum pse_device_ownership PseI2sOwn[2]; 440 enum pse_device_ownership PseSpiOwn[4]; 441 enum pse_device_ownership PseSpiCs0Own[4]; 442 enum pse_device_ownership PseSpiCs1Own[4]; 443 enum pse_device_ownership PseCanOwn[2]; 444 enum pse_device_ownership PsePwmOwn; 445 enum pse_device_ownership PseAdcOwn; 446 enum pse_device_ownership PseGbeOwn[MAX_PSE_TSN_PORTS]; 447 /* PSE devices sideband interrupt: Disable (0) / Enable (1) */ 448 bool PseDmaSbIntEn[3]; 449 bool PseUartSbIntEn[6]; 450 bool PseQepSbIntEn[4]; 451 bool PseI2cSbIntEn[8]; 452 bool PseI2sSbIntEn[2]; 453 bool PseSpiSbIntEn[4]; 454 bool PseCanSbIntEn[2]; 455 bool PseLh2PseSbIntEn; 456 bool PsePwmSbIntEn; 457 bool PseAdcSbIntEn; 458 /* PSE PWM native function: Disable (0) / Enable (1) */ 459 bool PsePwmPinEn[16]; 460 /* PSE Console Shell */ 461 bool PseShellEn; 462 463 /* 464 * DDR Frequency Limit 465 * 466 * Maximum Memory Frequency Selections in Mhz. 467 * Values: 1067, 1200, 1333, 1400, 1600, 1800, 1867, 2000, 2133, 468 * 2200, 2400, 2600, 2667, 2800, 2933, 3000, 3200, 3467, 469 * 3600, 3733, 4000, 4200, 4267 and 0 for Auto. 470 */ 471 uint16_t max_dram_speed_mts; 472 473 /* Disable L1 prefetcher */ 474 bool L1_prefetcher_disable; 475 476 /* Activate real time tuning according to the Real-Time Tuning Guide (doc #640979) */ 477 bool realtime_tuning_enable; 478 }; 479 480 typedef struct soc_intel_elkhartlake_config config_t; 481 482 #endif 483