1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <gpio.h>
4 #include <intelblocks/pcr.h>
5 #include <soc/pcr_ids.h>
6 #include <soc/pmc.h>
7
8 static const struct reset_mapping rst_map[] = {
9 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
10 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
11 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
12 };
13
14 static const struct reset_mapping rst_map_gpd[] = {
15 { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
16 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
17 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
18 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
19 };
20
21 /*
22 * The GPIO driver for Elkhartlake on Windows/Linux expects 32 GPIOs per pad
23 * group, regardless of whether or not there is a physical pad for each
24 * exposed GPIO number.
25 *
26 * This results in the OS having a sparse GPIO map, and devices that need
27 * to export an ACPI GPIO must use the OS expected number.
28 *
29 * Not all pins are usable as GPIO and those groups do not have a pad base.
30 *
31 * This layout matches the Linux kernel pinctrl map for MCC at:
32 * linux/drivers/pinctrl/intel/pinctrl-elkhartlake.c
33 */
34 static const struct pad_group ehl_community0_groups[] = {
35 INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_B23, 0), /* GPP_B */
36 INTEL_GPP(GPP_B0, GPIO_RSVD_0, GPIO_RSVD_1),
37 INTEL_GPP_BASE(GPP_B0, GPP_T0, GPP_T15, 32), /* GPP_T */
38 INTEL_GPP_BASE(GPP_B0, GPP_G0, GPIO_RSVD_2, 64), /* GPP_G */
39 };
40
41 static const struct pad_group ehl_community1_groups[] = {
42 INTEL_GPP_BASE(GPP_V0, GPP_V0, GPP_V15, 96), /* GPP_V */
43 INTEL_GPP_BASE(GPP_V0, GPP_H0, GPP_H23, 128), /* GPP_H */
44 INTEL_GPP_BASE(GPP_V0, GPP_D0, GPIO_RSVD_3, 160), /* GPP_D */
45 INTEL_GPP_BASE(GPP_V0, GPP_U0, GPP_U19, 192), /* GPP_U */
46 INTEL_GPP(GPP_V0, GPIO_RSVD_4, GPIO_RSVD_7),
47 INTEL_GPP_BASE(GPP_V0, VGPIO_0, VGPIO_39, 224), /* VGPIO */
48 };
49
50 /* This community is not visible to the OS */
51 static const struct pad_group ehl_community2_groups[] = {
52 INTEL_GPP(GPD0, GPD0, GPIO_RSVD_12), /* GPD */
53 };
54
55 static const struct pad_group ehl_community3_groups[] = {
56 INTEL_GPP(GPIO_RSVD_13, GPIO_RSVD_13, GPIO_RSVD_29),
57 INTEL_GPP_BASE(GPIO_RSVD_13, GPP_S0, GPP_S1, 288), /* GPP_S */
58 INTEL_GPP_BASE(GPIO_RSVD_13, GPP_A0, GPP_A23, 320), /* GPP_A */
59 INTEL_GPP(GPIO_RSVD_13, VGPIO_USB_0, VGPIO_USB_3),
60 };
61
62 static const struct pad_group ehl_community4_groups[] = {
63 INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 352), /* GPP_C */
64 INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F23, 384), /* GPP_F */
65 INTEL_GPP(GPP_C0, GPIO_RSVD_30, GPIO_RSVD_36),
66 INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E23, 416), /* GPP_E */
67 };
68
69 static const struct pad_group ehl_community5_groups[] = {
70 INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 448), /* GPP_R */
71 };
72
73 static const struct pad_community ehl_communities[TOTAL_GPIO_COMM] = {
74 /* GPP B, T, G */
75 [COMM_0] = {
76 .port = PID_GPIOCOM0,
77 .first_pad = GPIO_COM0_START,
78 .last_pad = GPIO_COM0_END,
79 .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
80 .pad_cfg_base = PAD_CFG_BASE,
81 .host_own_reg_0 = HOSTSW_OWN_REG_0,
82 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
83 .gpi_int_en_reg_0 = GPI_INT_EN_0,
84 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
85 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
86 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
87 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
88 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
89 .name = "GPP_BTG",
90 .acpi_path = "\\_SB.PCI0.GPIO",
91 .reset_map = rst_map,
92 .num_reset_vals = ARRAY_SIZE(rst_map),
93 .groups = ehl_community0_groups,
94 .num_groups = ARRAY_SIZE(ehl_community0_groups),
95 },
96 /* GPP V, H, D, U, VGPIO */
97 [COMM_1] = {
98 .port = PID_GPIOCOM1,
99 .first_pad = GPIO_COM1_START,
100 .last_pad = GPIO_COM1_END,
101 .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
102 .pad_cfg_base = PAD_CFG_BASE,
103 .host_own_reg_0 = HOSTSW_OWN_REG_0,
104 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
105 .gpi_int_en_reg_0 = GPI_INT_EN_0,
106 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
107 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
108 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
109 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
110 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
111 .name = "GPP_VHDU",
112 .acpi_path = "\\_SB.PCI0.GPIO",
113 .reset_map = rst_map,
114 .num_reset_vals = ARRAY_SIZE(rst_map),
115 .groups = ehl_community1_groups,
116 .num_groups = ARRAY_SIZE(ehl_community1_groups),
117 },
118 /* GPD */
119 [COMM_2] = {
120 .port = PID_GPIOCOM2,
121 .first_pad = GPIO_COM2_START,
122 .last_pad = GPIO_COM2_END,
123 .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
124 .pad_cfg_base = PAD_CFG_BASE,
125 .host_own_reg_0 = HOSTSW_OWN_REG_0,
126 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
127 .gpi_int_en_reg_0 = GPI_INT_EN_0,
128 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
129 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
130 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
131 .name = "GPD",
132 .acpi_path = "\\_SB.PCI0.GPIO",
133 .reset_map = rst_map_gpd,
134 .num_reset_vals = ARRAY_SIZE(rst_map_gpd),
135 .groups = ehl_community2_groups,
136 .num_groups = ARRAY_SIZE(ehl_community2_groups),
137 },
138 /* GPP S, A */
139 [COMM_3] = {
140 .port = PID_GPIOCOM3,
141 .first_pad = GPIO_COM3_START,
142 .last_pad = GPIO_COM3_END,
143 .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
144 .pad_cfg_base = PAD_CFG_BASE,
145 .host_own_reg_0 = HOSTSW_OWN_REG_0,
146 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
147 .gpi_int_en_reg_0 = GPI_INT_EN_0,
148 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
149 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
150 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
151 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
152 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
153 .name = "GPP_SA",
154 .acpi_path = "\\_SB.PCI0.GPIO",
155 .reset_map = rst_map,
156 .num_reset_vals = ARRAY_SIZE(rst_map),
157 .groups = ehl_community3_groups,
158 .num_groups = ARRAY_SIZE(ehl_community3_groups),
159 },
160 /* GPP C, F, E */
161 [COMM_4] = {
162 .port = PID_GPIOCOM4,
163 .first_pad = GPIO_COM4_START,
164 .last_pad = GPIO_COM4_END,
165 .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
166 .pad_cfg_base = PAD_CFG_BASE,
167 .host_own_reg_0 = HOSTSW_OWN_REG_0,
168 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
169 .gpi_int_en_reg_0 = GPI_INT_EN_0,
170 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
171 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
172 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
173 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
174 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
175 .name = "GPP_CFE",
176 .acpi_path = "\\_SB.PCI0.GPIO",
177 .reset_map = rst_map,
178 .num_reset_vals = ARRAY_SIZE(rst_map),
179 .groups = ehl_community4_groups,
180 .num_groups = ARRAY_SIZE(ehl_community4_groups),
181 },
182 /* GPP R*/
183 [COMM_5] = {
184 .port = PID_GPIOCOM5,
185 .first_pad = GPIO_COM5_START,
186 .last_pad = GPIO_COM5_END,
187 .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
188 .pad_cfg_base = PAD_CFG_BASE,
189 .host_own_reg_0 = HOSTSW_OWN_REG_0,
190 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
191 .gpi_int_en_reg_0 = GPI_INT_EN_0,
192 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
193 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
194 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
195 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
196 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
197 .name = "GPP_RR",
198 .acpi_path = "\\_SB.PCI0.GPIO",
199 .reset_map = rst_map,
200 .num_reset_vals = ARRAY_SIZE(rst_map),
201 .groups = ehl_community5_groups,
202 .num_groups = ARRAY_SIZE(ehl_community5_groups),
203 }
204 };
205
soc_gpio_get_community(size_t * num_communities)206 const struct pad_community *soc_gpio_get_community(size_t *num_communities)
207 {
208 *num_communities = ARRAY_SIZE(ehl_communities);
209 return ehl_communities;
210 }
211
soc_pmc_gpio_routes(size_t * num)212 const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
213 {
214 static const struct pmc_to_gpio_route routes[] = {
215 { PMC_GPP_B, GPP_B },
216 { PMC_GPP_T, GPP_T },
217 { PMC_GPP_D, GPP_D },
218 { PMC_GPP_A, GPP_A },
219 { PMC_GPP_R, GPP_R },
220 { PMC_GPP_V, GPP_V },
221 { PMC_GPD, GPD },
222 { PMC_GPP_H, GPP_H },
223 { PMC_GPP_U, GPP_U },
224 { PMC_VGPIO, VGPIO },
225 { PMC_GPP_F, GPP_F },
226 { PMC_GPP_C, GPP_C },
227 { PMC_GPP_E, GPP_E },
228 { PMC_GPP_G, GPP_G },
229 { PMC_GPP_S, GPP_S }
230 };
231
232 *num = ARRAY_SIZE(routes);
233 return routes;
234 }
235