1## SPDX-License-Identifier: GPL-2.0-only 2ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE),y) 3 4subdirs-y += romstage 5subdirs-y += ../../../cpu/intel/microcode 6subdirs-y += ../../../cpu/intel/turbo 7 8# all (bootblock, verstage, romstage, postcar, ramstage) 9all-y += gspi.c 10all-y += i2c.c 11all-y += pmutil.c 12all-y += spi.c 13all-y += uart.c 14 15bootblock-y += bootblock/bootblock.c 16bootblock-y += bootblock/pch.c 17bootblock-y += bootblock/report_platform.c 18bootblock-y += espi.c 19bootblock-y += gpio.c 20bootblock-y += p2sb.c 21 22romstage-y += espi.c 23romstage-y += gpio.c 24romstage-y += meminit.c 25romstage-y += pcie_rp.c 26romstage-y += reset.c 27 28ramstage-y += acpi.c 29ramstage-y += chip.c 30ramstage-y += cpu.c 31ramstage-y += elog.c 32ramstage-y += espi.c 33ramstage-y += finalize.c 34ramstage-y += fsp_params.c 35ramstage-y += gpio.c 36ramstage-y += graphics.c 37ramstage-y += lockdown.c 38ramstage-y += p2sb.c 39ramstage-y += pcie_rp.c 40ramstage-y += pmc.c 41ramstage-y += reset.c 42ramstage-y += systemagent.c 43ramstage-y += sd.c 44ramstage-y += xhci.c 45 46smm-y += gpio.c 47smm-y += p2sb.c 48smm-y += pmutil.c 49smm-y += smihandler.c 50smm-y += uart.c 51smm-y += elog.c 52smm-y += xhci.c 53 54verstage-y += gpio.c 55 56CPPFLAGS_common += -I$(src)/soc/intel/jasperlake 57CPPFLAGS_common += -I$(src)/soc/intel/jasperlake/include 58 59cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9c-00 60 61endif 62