1/* SPDX-License-Identifier: GPL-2.0-only */ 2 3#include <soc/gpe.h> 4 5/* 6 * JSL has 8 USB2 ports, so the USB3 PORTSC registers start at 7 * 0x480 + 8 * 0x10 = 0x500 8 */ 9#define JSL_PORTSCXUSB3_OFFSET 0x500 10 11/* Include UWES method for enabling USB wake */ 12#include <soc/intel/common/acpi/xhci_wake.asl> 13 14/* XHCI Controller 0:14.0 */ 15 16Device (XHCI) 17{ 18 Name (_ADR, 0x00140000) 19 20 Name (_PRW, Package () { GPE0_PME_B0, 3 }) 21 22 OperationRegion (XPRT, PCI_Config, 0x00, 0x100) 23 Field (XPRT, AnyAcc, NoLock, Preserve) 24 { 25 Offset (0x10), 26 , 16, 27 XMEM, 16, /* MEM_BASE */ 28 } 29 30 Method (_DSW, 3) 31 { 32 UWES ((\U2WE & 0xFF), PORTSCN_OFFSET, XMEM) 33 UWES ((\U3WE & 0x3F ), JSL_PORTSCXUSB3_OFFSET, XMEM) 34 } 35 36 Name (_S3D, 3) /* D3 supported in S3 */ 37 Name (_S0W, 3) /* D3 can wake device in S0 */ 38 Name (_S3W, 3) /* D3 can wake system from S3 */ 39 40 Method (_PS0, 0, Serialized) 41 { 42 43 } 44 45 Method (_PS3, 0, Serialized) 46 { 47 48 } 49 50 /* Root Hub for Jasperlake PCH */ 51 Device (RHUB) 52 { 53 Name (_ADR, 0) 54 55 /* USB2 */ 56 Device (HS01) { Name (_ADR, 1) } 57 Device (HS02) { Name (_ADR, 2) } 58 Device (HS03) { Name (_ADR, 3) } 59 Device (HS04) { Name (_ADR, 4) } 60 Device (HS05) { Name (_ADR, 5) } 61 Device (HS06) { Name (_ADR, 6) } 62 Device (HS07) { Name (_ADR, 7) } 63 Device (HS08) { Name (_ADR, 8) } 64 65 /* USB3 */ 66 Device (SS01) { Name (_ADR, 9) } 67 Device (SS02) { Name (_ADR, 10) } 68 Device (SS03) { Name (_ADR, 11) } 69 Device (SS04) { Name (_ADR, 12) } 70 Device (SS05) { Name (_ADR, 13) } 71 Device (SS06) { Name (_ADR, 14) } 72 } 73} 74