1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/pci.h>
4 #include <cpu/x86/mp.h>
5 #include <cpu/x86/msr.h>
6 #include <cpu/intel/smm_reloc.h>
7 #include <cpu/intel/turbo.h>
8 #include <cpu/intel/common/common.h>
9 #include <fsp/api.h>
10 #include <intelblocks/cpulib.h>
11 #include <intelblocks/mp_init.h>
12 #include <intelblocks/msr.h>
13 #include <soc/cpu.h>
14 #include <soc/msr.h>
15 #include <soc/pci_devs.h>
16 #include <soc/soc_chip.h>
17 #include <types.h>
18
cpu_soc_is_in_untrusted_mode(void)19 bool cpu_soc_is_in_untrusted_mode(void)
20 {
21 msr_t msr;
22
23 msr = rdmsr(MSR_BIOS_DONE);
24 return !!(msr.lo & ENABLE_IA_UNTRUSTED);
25 }
26
cpu_soc_bios_done(void)27 void cpu_soc_bios_done(void)
28 {
29 msr_t msr;
30
31 msr = rdmsr(MSR_BIOS_DONE);
32 msr.lo |= ENABLE_IA_UNTRUSTED;
33 wrmsr(MSR_BIOS_DONE, msr);
34 }
35
soc_fsp_load(void)36 static void soc_fsp_load(void)
37 {
38 fsps_load();
39 }
40
configure_misc(void)41 static void configure_misc(void)
42 {
43 msr_t msr;
44
45 config_t *conf = config_of_soc();
46
47 msr = rdmsr(IA32_MISC_ENABLE);
48 msr.lo |= (1 << 0); /* Fast String enable */
49 msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
50 wrmsr(IA32_MISC_ENABLE, msr);
51
52 /* Set EIST status */
53 cpu_set_eist(conf->eist_enable);
54
55 /* Disable Thermal interrupts */
56 msr.lo = 0;
57 msr.hi = 0;
58 wrmsr(IA32_THERM_INTERRUPT, msr);
59
60 /* Enable package critical interrupt only */
61 msr.lo = 1 << 4;
62 msr.hi = 0;
63 wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
64
65 /* Enable PROCHOT */
66 msr = rdmsr(MSR_POWER_CTL);
67 msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */
68 msr.lo |= (1 << 23); /* Lock it */
69 wrmsr(MSR_POWER_CTL, msr);
70 }
71
72 /* All CPUs including BSP will run the following function. */
soc_core_init(struct device * cpu)73 void soc_core_init(struct device *cpu)
74 {
75 /* Clear out pending MCEs */
76 /* TODO(adurbin): This should only be done on a cold boot. Also, some
77 * of these banks are core vs package scope. For now every CPU clears
78 * every bank. */
79 mca_configure();
80
81 enable_lapic_tpr();
82
83 /* Configure Enhanced SpeedStep and Thermal Sensors */
84 configure_misc();
85
86 enable_pm_timer_emulation();
87
88 /* Enable Direct Cache Access */
89 configure_dca_cap();
90
91 /* Set energy policy */
92 set_energy_perf_bias(ENERGY_POLICY_NORMAL);
93
94 /* Enable Turbo */
95 enable_turbo();
96 }
97
per_cpu_smm_trigger(void)98 static void per_cpu_smm_trigger(void)
99 {
100 /* Relocate the SMM handler. */
101 smm_relocate();
102 }
103
post_mp_init(void)104 static void post_mp_init(void)
105 {
106 /* Set Max Ratio */
107 cpu_set_max_ratio();
108
109 /*
110 * 1. Now that all APs have been relocated as well as the BSP let SMIs
111 * start flowing.
112 * 2. Skip enabling power button SMI and enable it after BS_CHIPS_INIT
113 * to avoid shutdown hang due to lack of init on certain IP in FSP-S.
114 */
115 global_smi_enable_no_pwrbtn();
116 }
117
118 static const struct mp_ops mp_ops = {
119 /*
120 * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP,
121 * that are set prior to ramstage.
122 * Real MTRRs programming are being done after resource allocation.
123 */
124 .pre_mp_init = soc_fsp_load,
125 .get_cpu_count = get_cpu_count,
126 .get_smm_info = smm_info,
127 .get_microcode_info = get_microcode_info,
128 .pre_mp_smm_init = smm_initialize,
129 .per_cpu_smm_trigger = per_cpu_smm_trigger,
130 .relocation_handler = smm_relocation_handler,
131 .post_mp_init = post_mp_init,
132 };
133
mp_init_cpus(struct bus * cpu_bus)134 void mp_init_cpus(struct bus *cpu_bus)
135 {
136 /* TODO: Handle mp_init_with_smm failure? */
137 mp_init_with_smm(cpu_bus, &mp_ops);
138
139 /* Thermal throttle activation offset */
140 configure_tcc_thermal_target();
141 }
142