1 /* SPDX-License-Identifier: GPL-2.0-only */
2 #include <assert.h>
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <fsp/api.h>
6 #include <fsp/ppi/mp_service_ppi.h>
7 #include <fsp/util.h>
8 #include <option.h>
9 #include <intelblocks/lpss.h>
10 #include <intelblocks/pmclib.h>
11 #include <intelblocks/xdci.h>
12 #include <intelpch/lockdown.h>
13 #include <soc/intel/common/vbt.h>
14 #include <soc/pci_devs.h>
15 #include <soc/ramstage.h>
16 #include <soc/soc_chip.h>
17 #include <string.h>
18 #include <types.h>
19
20 /*
21 * ME End of Post configuration
22 * 0 - Disable EOP.
23 * 1 - Send in PEI (Applicable for FSP in API mode)
24 * 2 - Send in DXE (Not applicable for FSP in API mode)
25 */
26 enum {
27 EOP_DISABLE = 0,
28 EOP_PEI = 1,
29 EOP_DXE = 2,
30 } EndOfPost;
31
parse_devicetree(FSP_S_CONFIG * params)32 static void parse_devicetree(FSP_S_CONFIG *params)
33 {
34 const struct soc_intel_jasperlake_config *config = config_of_soc();
35
36 /* LPSS controllers configuration */
37
38 /* I2C */
39 FSP_ARRAY_LOAD(params->SerialIoI2cMode, config->SerialIoI2cMode);
40
41 /* GSPI */
42 FSP_ARRAY_LOAD(params->SerialIoSpiMode, config->SerialIoGSpiMode);
43 FSP_ARRAY_LOAD(params->SerialIoSpiCsMode, config->SerialIoGSpiCsMode);
44 FSP_ARRAY_LOAD(params->SerialIoSpiCsState, config->SerialIoGSpiCsState);
45
46 /* UART */
47 FSP_ARRAY_LOAD(params->SerialIoUartMode, config->SerialIoUartMode);
48 }
49
50 /* UPD parameters to be initialized before SiliconInit */
platform_fsp_silicon_init_params_cb(FSPS_UPD * supd)51 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
52 {
53 unsigned int i;
54 FSP_S_CONFIG *params = &supd->FspsConfig;
55 struct soc_intel_jasperlake_config *config = config_of_soc();
56
57 /* Parse device tree and fill in FSP UPDs */
58 parse_devicetree(params);
59
60 /* Load VBT before devicetree-specific config. */
61 params->GraphicsConfigPtr = (uintptr_t)vbt_get();
62
63 /* Check if IGD is present and fill Graphics init param accordingly */
64 params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
65
66 params->PavpEnable = CONFIG(PAVP);
67
68 /* Use coreboot MP PPI services if Kconfig is enabled */
69 if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
70 params->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data();
71
72 /* Chipset Lockdown */
73 const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP;
74 params->PchLockDownGlobalSmi = lockdown_by_fsp;
75 params->PchLockDownBiosInterface = lockdown_by_fsp;
76 params->PchUnlockGpioPads = !lockdown_by_fsp;
77 params->RtcMemoryLock = lockdown_by_fsp;
78 params->SkipPamLock = !lockdown_by_fsp;
79
80 /* coreboot will send EOP before loading payload */
81 params->EndOfPostMessage = EOP_DISABLE;
82
83 /* Legacy 8254 timer support */
84 bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
85 params->Enable8254ClockGating = !use_8254;
86 params->Enable8254ClockGatingOnS3 = 1;
87
88 /*
89 * Legacy PM ACPI Timer (and TCO Timer)
90 * This *must* be 1 in any case to keep FSP from
91 * 1) enabling PM ACPI Timer emulation in uCode.
92 * 2) disabling the PM ACPI Timer.
93 * We handle both by ourself!
94 */
95 params->EnableTcoTimer = 1;
96
97 /* disable Legacy PME */
98 memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
99
100 /* Enable ClkReqDetect for enabled port */
101 memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect,
102 sizeof(config->PcieRpClkReqDetect));
103
104 /* USB configuration */
105 for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
106 params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
107 params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
108 params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
109 params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
110 params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
111
112 if (config->usb2_ports[i].enable)
113 params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
114 else
115 params->Usb2OverCurrentPin[i] = 0xff;
116 }
117
118 for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
119 params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
120 if (config->usb3_ports[i].enable) {
121 params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
122 } else {
123 params->Usb3OverCurrentPin[i] = 0xff;
124 }
125 if (config->usb3_ports[i].tx_de_emp) {
126 params->Usb3HsioTxDeEmphEnable[i] = 1;
127 params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
128 }
129 if (config->usb3_ports[i].tx_downscale_amp) {
130 params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
131 params->Usb3HsioTxDownscaleAmp[i] =
132 config->usb3_ports[i].tx_downscale_amp;
133 }
134 /* Enable USB3 Gen2 */
135 if (config->usb3_ports[i].gen2_tx_rate0_uniq_tran_enable) {
136 params->Usb3HsioTxRate0UniqTranEnable[i] = 1;
137 params->Usb3HsioTxRate0UniqTran[i] =
138 config->usb3_ports[i].gen2_tx_rate0_uniq_tran;
139 }
140 if (config->usb3_ports[i].gen2_tx_rate1_uniq_tran_enable) {
141 params->Usb3HsioTxRate1UniqTranEnable[i] = 1;
142 params->Usb3HsioTxRate1UniqTran[i] =
143 config->usb3_ports[i].gen2_tx_rate1_uniq_tran;
144 }
145 if (config->usb3_ports[i].gen2_tx_rate2_uniq_tran_enable) {
146 params->Usb3HsioTxRate2UniqTranEnable[i] = 1;
147 params->Usb3HsioTxRate2UniqTran[i] =
148 config->usb3_ports[i].gen2_tx_rate2_uniq_tran;
149 }
150 if (config->usb3_ports[i].gen2_tx_rate3_uniq_tran_enable) {
151 params->Usb3HsioTxRate3UniqTranEnable[i] = 1;
152 params->Usb3HsioTxRate3UniqTran[i] =
153 config->usb3_ports[i].gen2_tx_rate3_uniq_tran;
154 }
155 }
156
157 /* SATA */
158 params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA);
159 if (params->SataEnable) {
160 params->SataMode = config->SataMode;
161 params->SataSalpSupport = config->SataSalpSupport;
162
163 FSP_ARRAY_LOAD(params->SataPortsEnable, config->SataPortsEnable);
164 FSP_ARRAY_LOAD(params->SataPortsDevSlp, config->SataPortsDevSlp);
165 }
166
167 /* VR Configuration */
168 params->ImonSlope[0] = config->ImonSlope;
169 params->ImonOffset[0] = config->ImonOffset;
170
171 /* SDCard related configuration */
172 params->ScsSdCardEnabled = is_devfn_enabled(PCH_DEVFN_SDCARD);
173 if (params->ScsSdCardEnabled)
174 params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh;
175
176 /* Enable Processor Thermal Control */
177 params->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF);
178
179 /* Set TccActivationOffset */
180 params->TccActivationOffset = config->tcc_offset;
181
182 /* eMMC configuration */
183 params->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC);
184 if (params->ScsEmmcEnabled)
185 params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
186
187 params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG);
188
189 /* Provide correct UART number for FSP debug logs */
190 params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
191
192 /* Configure FIVR RFI related settings */
193 params->FivrRfiFrequency = config->FivrRfiFrequency;
194 params->FivrSpreadSpectrum = config->FivrSpreadSpectrum;
195
196 /* Apply minimum assertion width settings if non-zero */
197 if (config->PchPmSlpS3MinAssert)
198 params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert;
199 if (config->PchPmSlpS4MinAssert)
200 params->PchPmSlpS4MinAssert = config->PchPmSlpS4MinAssert;
201 if (config->PchPmSlpSusMinAssert)
202 params->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert;
203 if (config->PchPmSlpAMinAssert)
204 params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert;
205
206 /* Set Power Cycle Duration */
207 if (config->PchPmPwrCycDur)
208 params->PchPmPwrCycDur = get_pm_pwr_cyc_dur(config->PchPmSlpS4MinAssert,
209 config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert,
210 config->PchPmPwrCycDur);
211
212 /* Set PsysPmax */
213 if (config->PsysPmax) {
214 printk(BIOS_DEBUG, "PsysPmax = %dW\n", config->PsysPmax);
215 /* PsysPmax is in unit of 1/8 Watt */
216 params->PsysPmax = config->PsysPmax * 8;
217 }
218
219 /*
220 * Fill Acoustic noise mitigation related configuration
221 * JSL only has single VR domain (VCCIN VR), thus filling only index 0 for
222 * Slew rate and FastPkgCRamp for VR0 only.
223 */
224 params->AcousticNoiseMitigation = config->AcousticNoiseMitigation;
225
226 if (params->AcousticNoiseMitigation) {
227 params->FastPkgCRampDisable[0] = config->FastPkgCRampDisable;
228 params->SlowSlewRate[0] = config->SlowSlewRate;
229 params->PreWake = config->PreWake;
230 params->RampUp = config->RampUp;
231 params->RampDown = config->RampDown;
232 }
233
234 if (config->disable_external_bypass_vr) {
235 params->PchFivrExtV1p05RailEnabledStates = 0;
236 params->PchFivrExtVnnRailSxEnabledStates = 0;
237 params->PchFivrExtVnnRailEnabledStates = 0;
238 }
239
240 /*
241 * We intentionally want the default to be maximum value(0xff) to align with
242 * FSP, so we reserve the `0` value here to mean auto instead, and shift the
243 * other values by 1.
244 *
245 * Please refer to src/soc/intel/jasperlake/chip.h for the detail definition.
246 */
247 params->CdClock = config->cd_clock ? config->cd_clock - 1 : 0xff;
248
249 /* Override/Fill FSP Silicon Param for mainboard */
250 mainboard_silicon_init_params(params);
251 }
252
253 /* Mainboard GPIO Configuration */
mainboard_silicon_init_params(FSP_S_CONFIG * params)254 __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
255 {
256 printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
257 }
258