1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/pci_def.h>
4 #include <intelblocks/cse.h>
5 #include <intelblocks/smihandler.h>
6 #include <soc/soc_chip.h>
7 #include <soc/pci_devs.h>
8 #include <soc/pm.h>
9
10 /*
11 * Specific SOC SMI handler during ramstage finalize phase
12 *
13 * BIOS can't make CSME function disable as is due to POSTBOOT_SAI
14 * restriction in place from JSP chipset. Hence create SMI Handler to
15 * perform CSME function disabling logic during SMM mode.
16 */
smihandler_soc_at_finalize(void)17 void smihandler_soc_at_finalize(void)
18 {
19 if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
20 heci1_disable();
21 }
22
smihandler_soc_disable_busmaster(pci_devfn_t dev)23 int smihandler_soc_disable_busmaster(pci_devfn_t dev)
24 {
25 /* Skip disabling PMC bus master to keep IO decode enabled */
26 if (dev == PCH_DEV_PMC)
27 return 0;
28 return 1;
29 }
30
31 const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
32 [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
33 [APM_STS_BIT] = smihandler_southbridge_apmc,
34 [PM1_STS_BIT] = smihandler_southbridge_pm1,
35 [GPE0_STS_BIT] = smihandler_southbridge_gpe0,
36 [GPIO_STS_BIT] = smihandler_southbridge_gpi,
37 [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
38 [MCSMI_STS_BIT] = smihandler_southbridge_mc,
39 #if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
40 [TCO_STS_BIT] = smihandler_southbridge_tco,
41 #endif
42 [PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
43 [MONITOR_STS_BIT] = smihandler_southbridge_monitor,
44 };
45