1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/device.h>
4 #include <device/pci.h>
5 #include <fsp/api.h>
6 #include <fsp/util.h>
7 #include <gpio.h>
8 #include <intelblocks/acpi.h>
9 #include <intelblocks/cfg.h>
10 #include <intelblocks/cse.h>
11 #include <intelblocks/irq.h>
12 #include <intelblocks/itss.h>
13 #include <intelblocks/p2sb.h>
14 #include <intelblocks/pcie_rp.h>
15 #include <intelblocks/systemagent.h>
16 #include <intelblocks/tcss.h>
17 #include <intelblocks/xdci.h>
18 #include <soc/intel/common/reset.h>
19 #include <soc/intel/common/vbt.h>
20 #include <soc/iomap.h>
21 #include <soc/itss.h>
22 #include <soc/p2sb.h>
23 #include <soc/pci_devs.h>
24 #include <soc/pcie.h>
25 #include <soc/ramstage.h>
26 #include <soc/soc_chip.h>
27 #include <soc/tcss.h>
28
29 #if CONFIG(HAVE_ACPI_TABLES)
soc_acpi_name(const struct device * dev)30 const char *soc_acpi_name(const struct device *dev)
31 {
32 if (dev->path.type == DEVICE_PATH_DOMAIN)
33 return "PCI0";
34
35 if (dev->path.type == DEVICE_PATH_USB) {
36 switch (dev->path.usb.port_type) {
37 case 0:
38 /* Root Hub */
39 return "RHUB";
40 case 2:
41 /* USB2 ports */
42 switch (dev->path.usb.port_id) {
43 case 0: return "HS01";
44 case 1: return "HS02";
45 case 2: return "HS03";
46 case 3: return "HS04";
47 case 4: return "HS05";
48 case 5: return "HS06";
49 case 6: return "HS07";
50 case 7: return "HS08";
51 case 8: return "HS09";
52 case 9: return "HS10";
53 }
54 break;
55 case 3:
56 /* USB3 ports */
57 switch (dev->path.usb.port_id) {
58 case 0: return "SS01";
59 case 1: return "SS02";
60 case 2: return "SS03";
61 case 3: return "SS04";
62 }
63 break;
64 }
65 printk(BIOS_DEBUG, "dev->path.type=%x\n", dev->path.usb.port_type);
66 return NULL;
67 }
68 if (dev->path.type != DEVICE_PATH_PCI) {
69 printk(BIOS_DEBUG, "dev->path.type=%x\n", dev->path.type);
70 return NULL;
71 }
72
73 switch (dev->path.pci.devfn) {
74 case PCI_DEVFN_ROOT: return "MCHC";
75 case PCI_DEVFN_IGD: return "GFX0";
76 case PCI_DEVFN_TCSS_XHCI: return "TXHC";
77 case PCI_DEVFN_TCSS_XDCI: return "TXDC";
78 case PCI_DEVFN_TCSS_DMA0: return "TDM0";
79 case PCI_DEVFN_TCSS_DMA1: return "TDM1";
80 case PCI_DEVFN_TBT0: return "TRP0";
81 case PCI_DEVFN_TBT1: return "TRP1";
82 case PCI_DEVFN_TBT2: return "TRP2";
83 case PCI_DEVFN_TBT3: return "TRP3";
84 case PCI_DEVFN_IPU: return "IPU0";
85 case PCI_DEVFN_ISH: return "ISHB";
86 case PCI_DEVFN_GNA: return "GNA";
87 case PCI_DEVFN_XHCI: return "XHCI";
88 case PCI_DEVFN_I2C0: return "I2C0";
89 case PCI_DEVFN_I2C1: return "I2C1";
90 case PCI_DEVFN_I2C2: return "I2C2";
91 case PCI_DEVFN_I2C3: return "I2C3";
92 case PCI_DEVFN_I2C4: return "I2C4";
93 case PCI_DEVFN_I2C5: return "I2C5";
94 case PCI_DEVFN_SATA: return "SATA";
95 case PCI_DEVFN_PCIE1: return "RP01";
96 case PCI_DEVFN_PCIE2: return "RP02";
97 case PCI_DEVFN_PCIE3: return "RP03";
98 case PCI_DEVFN_PCIE4: return "RP04";
99 case PCI_DEVFN_PCIE5: return "RP05";
100 case PCI_DEVFN_PCIE6: return "RP06";
101 case PCI_DEVFN_PCIE7: return "RP07";
102 case PCI_DEVFN_PCIE8: return "RP08";
103 case PCI_DEVFN_PCIE9: return "RP09";
104 case PCI_DEVFN_PCIE10: return "RP10";
105 case PCI_DEVFN_PCIE11: return "RP11";
106 case PCI_DEVFN_PCIE12: return "RP12";
107 case PCI_DEVFN_PMC: return "PMC";
108 case PCI_DEVFN_UART0: return "UAR0";
109 case PCI_DEVFN_UART1: return "UAR1";
110 case PCI_DEVFN_UART2: return "UAR2";
111 case PCI_DEVFN_GSPI0: return "SPI0";
112 case PCI_DEVFN_GSPI1: return "SPI1";
113 case PCI_DEVFN_GSPI2: return "SPI2";
114 /* Keeping ACPI device name coherent with ec.asl */
115 case PCI_DEVFN_ESPI: return "LPCB";
116 case PCI_DEVFN_HDA: return "HDAS";
117 case PCI_DEVFN_SMBUS: return "SBUS";
118 case PCI_DEVFN_GBE: return "GLAN";
119 }
120 printk(BIOS_DEBUG, "Missing ACPI Name for PCI: 00:%02x.%01x\n",
121 PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
122 return NULL;
123 }
124 #endif
125
126 #if CONFIG(SOC_INTEL_STORE_ISH_FW_VERSION)
127 /* SoC override API to identify if ISH Firmware existed inside CSE FPT */
soc_is_ish_partition_enabled(void)128 bool soc_is_ish_partition_enabled(void)
129 {
130 struct device *ish = pcidev_path_on_root(PCI_DEVFN_ISH);
131 uint16_t ish_pci_id = ish ? pci_read_config16(ish, PCI_DEVICE_ID) : 0xFFFF;
132
133 if (ish_pci_id == 0xFFFF)
134 return false;
135
136 return true;
137 }
138 #endif
139
140 /* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */
soc_fill_gpio_pm_configuration(void)141 static void soc_fill_gpio_pm_configuration(void)
142 {
143 uint8_t value[TOTAL_GPIO_COMM];
144 const config_t *config = config_of_soc();
145
146 if (config->gpio_override_pm)
147 memcpy(value, config->gpio_pm, sizeof(value));
148 else
149 memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(value));
150
151 gpio_pm_configure(value, TOTAL_GPIO_COMM);
152 }
153
154 /* Enable tracehub in device tree */
soc_enable_tracehub(void)155 static void soc_enable_tracehub(void)
156 {
157 struct device *dev;
158
159 dev = pcidev_path_on_root(PCI_DEVFN_NPK);
160 if (dev) {
161 dev->enabled = 1;
162 printk(BIOS_DEBUG, "Tracehub is enabled.\n");
163 }
164 }
165
soc_init_pre_device(void * chip_info)166 void soc_init_pre_device(void *chip_info)
167 {
168 config_t *config = config_of_soc();
169
170 /* Validate TBT image authentication */
171 config->tbt_authentication = ioe_p2sb_sbi_read(PID_IOM,
172 IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION;
173
174 if (CONFIG(SOC_INTEL_COMMON_BLOCK_TRACEHUB))
175 soc_enable_tracehub();
176
177 /* Perform silicon specific init. */
178 fsp_silicon_init();
179
180 /* Display FIRMWARE_VERSION_INFO_HOB */
181 fsp_display_fvi_version_hob();
182
183 soc_fill_gpio_pm_configuration();
184
185 /* Swap enabled PCI ports in device tree if needed. */
186 pcie_rp_update_devicetree(get_pcie_rp_table());
187
188 /* Swap enabled TBT root ports in device tree if needed. */
189 pcie_rp_update_devicetree(get_tbt_pcie_rp_table());
190
191 /*
192 * Earlier when coreboot used to send EOP at late as possible caused
193 * issue of delayed response from CSE since CSE was busy loading payload.
194 * To resolve the issue, EOP should be sent earlier than current sequence
195 * in the boot sequence at BS_DEV_INIT.
196 *
197 * Intel CSE team recommends to send EOP close to FW init (between FSP-S
198 * exit and current boot sequence) to reduce message response time from
199 * CSE hence moving sending EOP to earlier stage.
200 */
201 if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY) ||
202 CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) {
203 printk(BIOS_INFO, "Sending EOP early from SoC\n");
204 cse_send_end_of_post();
205 }
206 }
207
cpu_fill_ssdt(const struct device * dev)208 static void cpu_fill_ssdt(const struct device *dev)
209 {
210 if (!generate_pin_irq_map())
211 printk(BIOS_ERR, "Failed to generate ACPI _PRT table!\n");
212
213 generate_cpu_entries(dev);
214 }
215
cpu_set_north_irqs(struct device * dev)216 static void cpu_set_north_irqs(struct device *dev)
217 {
218 irq_program_non_pch();
219 }
220
221 static struct device_operations pci_domain_ops = {
222 .read_resources = &pci_domain_read_resources,
223 .set_resources = &pci_domain_set_resources,
224 .scan_bus = &pci_host_bridge_scan_bus,
225 #if CONFIG(HAVE_ACPI_TABLES)
226 .acpi_name = &soc_acpi_name,
227 .acpi_fill_ssdt = ssdt_set_above_4g_pci,
228 #endif
229 };
230
231 static struct device_operations cpu_bus_ops = {
232 .read_resources = noop_read_resources,
233 .set_resources = noop_set_resources,
234 .enable_resources = cpu_set_north_irqs,
235 #if CONFIG(HAVE_ACPI_TABLES)
236 .acpi_fill_ssdt = cpu_fill_ssdt,
237 #endif
238 };
239
soc_enable(struct device * dev)240 static void soc_enable(struct device *dev)
241 {
242 /*
243 * Set the operations if it is a special bus type or a hidden PCI
244 * device.
245 */
246 if (dev->path.type == DEVICE_PATH_DOMAIN)
247 dev->ops = &pci_domain_ops;
248 else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
249 dev->ops = &cpu_bus_ops;
250 else if (dev->path.type == DEVICE_PATH_PCI &&
251 dev->path.pci.devfn == PCI_DEVFN_PMC)
252 dev->ops = &pmc_ops;
253 else if (dev->path.type == DEVICE_PATH_PCI &&
254 dev->path.pci.devfn == PCI_DEVFN_IOE_PMC)
255 dev->ops = &ioe_pmc_ops;
256 else if (dev->path.type == DEVICE_PATH_PCI &&
257 dev->path.pci.devfn == PCI_DEVFN_P2SB)
258 dev->ops = &soc_p2sb_ops;
259 else if (dev->path.type == DEVICE_PATH_PCI &&
260 dev->path.pci.devfn == PCI_DEVFN_IOE_P2SB)
261 dev->ops = &ioe_p2sb_ops;
262 else if (dev->path.type == DEVICE_PATH_GPIO)
263 block_gpio_enable(dev);
264 }
265
soc_init_final_device(void * chip_info)266 static void soc_init_final_device(void *chip_info)
267 {
268 uint32_t reset_status = fsp_get_pch_reset_status();
269
270 if (reset_status == FSP_SUCCESS)
271 return;
272
273 /* Handle any pending reset request from previously executed FSP APIs */
274 fsp_handle_reset(reset_status);
275
276 /* Control shouldn't return here */
277 die_with_post_code(POSTCODE_HW_INIT_FAILURE,
278 "Failed to handle the FSP reset request with error 0x%08x\n", reset_status);
279 }
280
281 struct chip_operations soc_intel_meteorlake_ops = {
282 .name = "Intel Meteorlake",
283 .enable_dev = &soc_enable,
284 .init = &soc_init_pre_device,
285 .final = &soc_init_final_device,
286 };
287