1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <arch/bert_storage.h>
4 #include <console/console.h>
5 #include <cpu/cpu.h>
6 #include <cpu/intel/cpu_ids.h>
7 #include <delay.h>
8 #include <device/pci_ops.h>
9 #include <intelblocks/crashlog.h>
10 #include <intelblocks/pmc_ipc.h>
11 #include <soc/crashlog.h>
12 #include <soc/iomap.h>
13 #include <soc/pci_devs.h>
14 #include <string.h>
15
16 #define CONTROL_INTERFACE_OFFSET 0x5
17 #define CRASHLOG_NODES_COUNT 0x2 /* Crashlog record of PUNIT & Uncore of SoC-N Die */
18 #define CRASHLOG_PUNIT_STORAGE_OFF_MASK BIT(24)
19 #define CRASHLOG_RE_ARM_STATUS_MASK BIT(25)
20 #define CRASHLOG_CONSUMED_MASK BIT(31)
21
22 /* global crashLog info */
23 static bool m_pmc_crashLog_support;
24 static bool m_pmc_crashLog_present;
25 static bool m_cpu_crashLog_support;
26 static bool m_cpu_crashLog_present;
27 static u32 m_pmc_crashLog_size;
28 static u32 m_cpu_crashLog_size;
29 static u32 cpu_crash_version;
30 static pmc_ipc_discovery_buf_t discovery_buf;
31 static pmc_crashlog_desc_table_t descriptor_table;
32 static tel_crashlog_devsc_cap_t cpu_cl_devsc_cap;
33 static cpu_crashlog_discovery_table_t cpu_cl_disc_tab;
34 static uintptr_t disc_tab_addr;
35
get_disc_tab_header(void)36 static u64 get_disc_tab_header(void)
37 {
38 return read64p(disc_tab_addr);
39 }
40
41 /* Get the SRAM BAR. */
get_sram_bar(pci_devfn_t sram_devfn)42 static uintptr_t get_sram_bar(pci_devfn_t sram_devfn)
43 {
44 uintptr_t sram_bar;
45 const struct device *dev;
46 struct resource *res;
47
48 dev = pcidev_path_on_root(sram_devfn);
49 if (!dev) {
50 printk(BIOS_ERR, "device: 0x%x not found!\n", sram_devfn);
51 return 0;
52 }
53
54 res = probe_resource(dev, PCI_BASE_ADDRESS_0);
55 if (!res) {
56 printk(BIOS_ERR, "SOC SRAM device not found!\n");
57 return 0;
58 }
59
60 /* Get the base address of the resource */
61 sram_bar = res->base;
62
63 return sram_bar;
64 }
65
configure_sram(const struct device * sram_dev,uintptr_t base_addr)66 static void configure_sram(const struct device *sram_dev, uintptr_t base_addr)
67 {
68 pci_update_config16(sram_dev, PCI_COMMAND, ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY), 0);
69
70 /* Program BAR 0 and enable command register memory space decoding */
71 pci_write_config32(sram_dev, PCI_BASE_ADDRESS_0, base_addr);
72 pci_or_config16(sram_dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
73 }
74
cl_get_pmc_sram_data(cl_node_t * head)75 void cl_get_pmc_sram_data(cl_node_t *head)
76 {
77 uintptr_t pmc_sram_base = cl_get_cpu_tmp_bar();
78 uintptr_t ioe_sram_base = get_sram_bar(PCI_DEVFN_IOE_SRAM);
79 u32 pmc_crashLog_size = cl_get_pmc_record_size();
80 cl_node_t *cl_cur = head;
81
82 if (!pmc_crashLog_size) {
83 printk(BIOS_ERR, "No PMC crashlog records\n");
84 return;
85 }
86
87 if (!pmc_sram_base) {
88 printk(BIOS_ERR, "PMC SRAM base not valid\n");
89 return;
90 }
91
92 if (!ioe_sram_base) {
93 printk(BIOS_ERR, "IOE SRAM base not valid\n");
94 return;
95 }
96
97 configure_sram(PCI_DEV_IOE_SRAM, ioe_sram_base);
98
99 if (!cl_pmc_sram_has_mmio_access())
100 return;
101
102 if (!cl_ioe_sram_has_mmio_access())
103 return;
104
105 printk(BIOS_DEBUG, "PMC crashLog size : 0x%x\n", pmc_crashLog_size);
106
107 /* goto tail node */
108 while (cl_cur && cl_cur->next) {
109 cl_cur = cl_cur->next;
110 }
111
112 /* process crashlog records */
113 for (int i = 0; i < descriptor_table.numb_regions + 1; i++) {
114 uintptr_t sram_base = 0;
115 bool pmc_sram = true;
116 printk(BIOS_DEBUG, "Region[0x%x].Tag=0x%x offset=0x%x, size=0x%x\n",
117 i,
118 descriptor_table.regions[i].bits.assign_tag,
119 descriptor_table.regions[i].bits.offset,
120 descriptor_table.regions[i].bits.size);
121
122 if (!descriptor_table.regions[i].bits.size)
123 continue;
124
125 /*
126 * Region with metadata TAG contains information about BDF entry for SOC PMC SRAM
127 * and IOE SRAM. We don't need to parse this as we already define BDFs in
128 * soc/pci_devs.h for these SRAMs. Also we need to skip this region as it does not
129 * contain any crashlog data.
130 */
131 if (descriptor_table.regions[i].bits.assign_tag ==
132 CRASHLOG_DESCRIPTOR_TABLE_TAG_META) {
133 pmc_crashLog_size -= descriptor_table.regions[i].bits.size *
134 sizeof(u32);
135 printk(BIOS_DEBUG, "Found metadata tag. PMC crashlog size adjusted to: 0x%x\n",
136 pmc_crashLog_size);
137 continue;
138 } else {
139 if (descriptor_table.regions[i].bits.assign_tag ==
140 CRASHLOG_DESCRIPTOR_TABLE_TAG_SOC)
141 sram_base = pmc_sram_base;
142 else if (descriptor_table.regions[i].bits.assign_tag ==
143 CRASHLOG_DESCRIPTOR_TABLE_TAG_IOE)
144 sram_base = ioe_sram_base;
145 else
146 continue;
147
148 cl_node_t *cl_node = malloc_cl_node(descriptor_table.regions[i].bits.size);
149
150 if (!cl_node) {
151 printk(BIOS_DEBUG, "failed to allocate cl_node [region = %d]\n", i);
152 goto pmc_send_re_arm_after_reset;
153 }
154
155 if (cl_copy_data_from_sram(sram_base,
156 descriptor_table.regions[i].bits.offset,
157 descriptor_table.regions[i].bits.size,
158 cl_node->data,
159 i,
160 pmc_sram)) {
161 cl_cur->next = cl_node;
162 cl_cur = cl_cur->next;
163 } else {
164 /* coping data from sram failed */
165 pmc_crashLog_size -= descriptor_table.regions[i].bits.size *
166 sizeof(u32);
167 printk(BIOS_DEBUG, "PMC crashlog size adjusted to: 0x%x\n",
168 pmc_crashLog_size);
169 /* free cl_node */
170 free_cl_node(cl_node);
171 }
172 }
173 }
174
175 update_new_pmc_crashlog_size(&pmc_crashLog_size);
176
177 pmc_send_re_arm_after_reset:
178 /* when bit 7 of discov cmd resp is set -> bit 2 of size field */
179 cl_pmc_re_arm_after_reset();
180
181 /* Clear the SSRAM region after copying the error log */
182 cl_pmc_clear();
183 }
184
pmc_cl_discovery(void)185 bool pmc_cl_discovery(void)
186 {
187 uintptr_t bar_addr = 0, desc_table_addr = 0;
188
189 const struct pmc_ipc_buffer req = { 0 };
190 struct pmc_ipc_buffer res;
191 uint32_t cmd_reg;
192 int r;
193
194 cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_CRASHLOG,
195 PMC_IPC_CMD_ID_CRASHLOG_DISCOVERY,
196 PMC_IPC_CMD_SIZE_SHIFT);
197 printk(BIOS_DEBUG, "cmd_reg from pmc_make_ipc_cmd %d in %s\n", cmd_reg, __func__);
198
199 r = pmc_send_ipc_cmd(cmd_reg, &req, &res);
200
201 if (r < 0) {
202 printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n", __func__);
203 return false;
204 }
205 discovery_buf.conv_val_64_bits = ((u64)res.buf[1] << 32) | res.buf[0];
206
207 if ((discovery_buf.conv_bits64.supported != 1) ||
208 (discovery_buf.conv_bits64.discov_mechanism == 0) ||
209 (discovery_buf.conv_bits64.crash_dis_sts == 1)) {
210 printk(BIOS_INFO, "PCH crashlog feature not supported.\n");
211 m_pmc_crashLog_support = false;
212 m_pmc_crashLog_size = 0;
213 printk(BIOS_DEBUG, "discovery_buf supported: %d, mechanism: %d, CrashDisSts: %d\n",
214 discovery_buf.conv_bits64.supported,
215 discovery_buf.conv_bits64.discov_mechanism,
216 discovery_buf.conv_bits64.crash_dis_sts);
217 return false;
218 }
219
220 printk(BIOS_INFO, "PMC crashlog feature is supported.\n");
221 m_pmc_crashLog_support = true;
222
223 /* Program BAR 0 and enable command register memory space decoding */
224 bar_addr = get_sram_bar(PCI_DEVFN_SRAM);
225 if (bar_addr == 0) {
226 printk(BIOS_ERR, "PCH SRAM not available, crashlog feature can't be enabled.\n");
227 return false;
228 }
229
230 configure_sram(PCI_DEV_SRAM, bar_addr);
231
232 desc_table_addr = bar_addr + discovery_buf.conv_bits64.desc_tabl_offset;
233 m_pmc_crashLog_size = pmc_cl_gen_descriptor_table(desc_table_addr,
234 &descriptor_table);
235 printk(BIOS_DEBUG, "PMC CrashLog size in discovery mode: 0x%X\n",
236 m_pmc_crashLog_size);
237 m_pmc_crashLog_present = m_pmc_crashLog_size > 0;
238
239 return true;
240 }
241
cl_get_cpu_bar_addr(void)242 uintptr_t cl_get_cpu_bar_addr(void)
243 {
244 uintptr_t base_addr = 0;
245 if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) {
246 base_addr = pci_read_config32(PCI_DEV_TELEMETRY, PCI_BASE_ADDRESS_0) &
247 ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
248 } else if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR1) {
249 base_addr = pci_read_config32(PCI_DEV_TELEMETRY, PCI_BASE_ADDRESS_1) &
250 ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
251 } else {
252 printk(BIOS_ERR, "Invalid TEL_CFG_BAR value %d, discovery failure expected.\n",
253 cpu_cl_devsc_cap.discovery_data.fields.t_bir_q);
254 }
255
256 return base_addr;
257 }
258
cl_get_cpu_tmp_bar(void)259 uintptr_t cl_get_cpu_tmp_bar(void)
260 {
261 return get_sram_bar(PCI_DEVFN_SRAM);
262 }
263
cl_pmc_sram_has_mmio_access(void)264 bool cl_pmc_sram_has_mmio_access(void)
265 {
266 if (pci_read_config16(PCI_DEV_SRAM, PCI_VENDOR_ID) == 0xFFFF) {
267 printk(BIOS_ERR, "PMC SSRAM PCI device disabled. Can be enabled in device tree.\n");
268 return false;
269 }
270
271 return true;
272 }
273
cl_ioe_sram_has_mmio_access(void)274 bool cl_ioe_sram_has_mmio_access(void)
275 {
276 if (pci_read_config16(PCI_DEV_IOE_SRAM, PCI_VENDOR_ID) == 0xFFFF) {
277 printk(BIOS_ERR, "IOE SSRAM PCI device disabled. Can be enabled in device tree.\n");
278 return false;
279 }
280 return true;
281 }
282
cpu_cl_get_capability(tel_crashlog_devsc_cap_t * cl_devsc_cap)283 static bool cpu_cl_get_capability(tel_crashlog_devsc_cap_t *cl_devsc_cap)
284 {
285 cl_devsc_cap->cap_data.data = pci_read_config32(PCI_DEV_TELEMETRY,
286 TEL_DVSEC_OFFSET + TEL_DVSEC_PCIE_CAP_ID);
287 if (cl_devsc_cap->cap_data.fields.pcie_cap_id != TELEMETRY_EXTENDED_CAP_ID) {
288 printk(BIOS_DEBUG, "Read ID for Telemetry: 0x%x differs from expected: 0x%x\n",
289 cl_devsc_cap->cap_data.fields.pcie_cap_id, TELEMETRY_EXTENDED_CAP_ID);
290 return false;
291 }
292
293 /* walk through the entries until crashLog entry */
294 cl_devsc_cap->devsc_data.data_32[1] = pci_read_config32(PCI_DEV_TELEMETRY, TEL_DVSEV_ID);
295 int new_offset = 0;
296 while (cl_devsc_cap->devsc_data.fields.devsc_id != CRASHLOG_DVSEC_ID) {
297 if (cl_devsc_cap->cap_data.fields.next_cap_offset == 0
298 || cl_devsc_cap->cap_data.fields.next_cap_offset == 0xFFFF) {
299 printk(BIOS_DEBUG, "Read invalid pcie_cap_id value: 0x%x\n",
300 cl_devsc_cap->cap_data.fields.pcie_cap_id);
301 return false;
302 }
303 new_offset = cl_devsc_cap->cap_data.fields.next_cap_offset;
304 cl_devsc_cap->cap_data.data = pci_read_config32(PCI_DEV_TELEMETRY,
305 new_offset + TEL_DVSEC_PCIE_CAP_ID);
306 cl_devsc_cap->devsc_data.data_32[1] = pci_read_config32(PCI_DEV_TELEMETRY,
307 new_offset + TEL_DVSEV_ID);
308 }
309 cpu_crash_version = cl_devsc_cap->devsc_data.fields.devsc_ver;
310
311 cl_devsc_cap->discovery_data.data = pci_read_config32(PCI_DEV_TELEMETRY, new_offset
312 + TEL_DVSEV_DISCOVERY_TABLE_OFFSET);
313
314 return true;
315 }
316
get_disc_table_offset(void)317 static u32 get_disc_table_offset(void)
318 {
319 u32 offset = cpu_cl_devsc_cap.discovery_data.fields.discovery_table_offset;
320 if (cpu_get_cpuid() >= CPUID_METEORLAKE_B0) {
321 offset <<= 3;
322 printk(BIOS_DEBUG, "adjusted cpu discovery table offset: 0x%x\n", offset);
323 }
324
325 return offset;
326 }
327
is_crashlog_data_valid(u32 dw0)328 static bool is_crashlog_data_valid(u32 dw0)
329 {
330 return (dw0 != 0x0 && dw0 != INVALID_CRASHLOG_RECORD);
331 }
332
cpu_cl_gen_discovery_table(void)333 static bool cpu_cl_gen_discovery_table(void)
334 {
335 uintptr_t bar_addr = cl_get_cpu_bar_addr();
336
337 if (!bar_addr)
338 return false;
339
340 disc_tab_addr = bar_addr + get_disc_table_offset();
341 memset(&cpu_cl_disc_tab, 0, sizeof(cpu_crashlog_discovery_table_t));
342 cpu_cl_disc_tab.header.data = get_disc_tab_header();
343 /* Check both 32 bit header data and status register for non-zero values */
344 if ((!is_crashlog_data_valid(cpu_cl_disc_tab.header.data & 0xFFFFFFFF)) &&
345 (!is_crashlog_data_valid((cpu_cl_disc_tab.header.data) >> 32)))
346 return false;
347
348 u32 cur_offset = 0;
349 cpu_cl_disc_tab.header.fields.count = CRASHLOG_NODES_COUNT;
350 printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer count: 0x%x\n",
351 cpu_cl_disc_tab.header.fields.count);
352 for (int i = 0; i < cpu_cl_disc_tab.header.fields.count; i++) {
353 cur_offset = 8 + 24 * i;
354 u32 cl_buffer_size = read32p(disc_tab_addr + cur_offset + 4);
355 /* Check for buffer size */
356 if (!(is_crashlog_data_valid(cl_buffer_size)))
357 continue;
358
359 u32 dw0 = read32p(disc_tab_addr + cur_offset);
360 if (dw0 & CRASHLOG_CONSUMED_MASK) {
361 printk(BIOS_DEBUG, "cpu crashlog records already consumed."
362 "id: 0x%x dw0: 0x%x\n", i, dw0);
363 break;
364 }
365
366 cpu_cl_disc_tab.buffers[i].data = read64p(disc_tab_addr + cur_offset);
367 printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer: 0x%x size: "
368 "0x%x offset: 0x%x\n", i, cpu_cl_disc_tab.buffers[i].fields.size,
369 cpu_cl_disc_tab.buffers[i].fields.offset);
370 m_cpu_crashLog_size += cpu_cl_disc_tab.buffers[i].fields.size * sizeof(u32);
371 }
372
373 if (m_cpu_crashLog_size > 0)
374 m_cpu_crashLog_present = true;
375 else
376 m_cpu_crashLog_present = false;
377
378 return true;
379 }
380
cpu_cl_discovery(void)381 bool cpu_cl_discovery(void)
382 {
383 memset(&cpu_cl_devsc_cap, 0, sizeof(tel_crashlog_devsc_cap_t));
384
385 if (!cpu_cl_get_capability(&cpu_cl_devsc_cap)) {
386 printk(BIOS_ERR, "CPU crashlog capability not found.\n");
387 m_cpu_crashLog_support = false;
388 return false;
389 }
390
391 m_cpu_crashLog_support = true;
392
393 if (!cpu_cl_gen_discovery_table()) {
394 printk(BIOS_ERR, "CPU crashlog discovery table not valid.\n");
395 m_cpu_crashLog_present = false;
396 return false;
397 }
398
399 return true;
400 }
401
reset_discovery_buffers(void)402 void reset_discovery_buffers(void)
403 {
404 memset(&discovery_buf, 0, sizeof(pmc_ipc_discovery_buf_t));
405 memset(&descriptor_table, 0, sizeof(pmc_crashlog_desc_table_t));
406 memset(&cpu_cl_devsc_cap, 0, sizeof(tel_crashlog_devsc_cap_t));
407 }
408
cl_get_total_data_size(void)409 int cl_get_total_data_size(void)
410 {
411 printk(BIOS_DEBUG, "crashlog size:pmc-0x%x, cpu-0x%x\n",
412 m_pmc_crashLog_size, m_cpu_crashLog_size);
413 return m_pmc_crashLog_size + m_cpu_crashLog_size;
414 }
415
get_control_status_interface(void)416 static uintptr_t get_control_status_interface(void)
417 {
418 if (disc_tab_addr)
419 return (disc_tab_addr + CONTROL_INTERFACE_OFFSET * sizeof(u32));
420 return 0;
421 }
422
cpu_cl_clear_data(void)423 int cpu_cl_clear_data(void)
424 {
425 return 0;
426 }
427
wait_and_check(u32 bit_mask)428 static bool wait_and_check(u32 bit_mask)
429 {
430 u32 stall_cnt = 0;
431
432 do {
433 cpu_cl_disc_tab.header.data = get_disc_tab_header();
434 udelay(CPU_CRASHLOG_WAIT_STALL);
435 stall_cnt++;
436 } while (((cpu_cl_disc_tab.header.data & bit_mask) == 0) &&
437 ((stall_cnt * CPU_CRASHLOG_WAIT_STALL) < CPU_CRASHLOG_WAIT_TIMEOUT));
438
439 return (cpu_cl_disc_tab.header.data & bit_mask);
440 }
441
cpu_cl_rearm(void)442 void cpu_cl_rearm(void)
443 {
444 uintptr_t ctrl_sts_intfc_addr = get_control_status_interface();
445
446 if (!ctrl_sts_intfc_addr) {
447 printk(BIOS_ERR, "CPU crashlog control and status interface address not valid\n");
448 return;
449 }
450
451 /* Rearm the CPU crashlog. Crashlog does not get collected if rearming fails */
452 cl_punit_control_interface_t punit_ctrl_intfc;
453 memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t));
454 punit_ctrl_intfc.fields.set_re_arm = 1;
455 write32p(ctrl_sts_intfc_addr, punit_ctrl_intfc.data);
456
457 if (!wait_and_check(CRASHLOG_RE_ARM_STATUS_MASK))
458 printk(BIOS_ERR, "CPU crashlog re_arm not asserted\n");
459 else
460 printk(BIOS_DEBUG, "CPU crashlog re_arm asserted\n");
461 }
462
cpu_cl_cleanup(void)463 void cpu_cl_cleanup(void)
464 {
465 /* Perform any SOC specific cleanup after reading the crashlog data from SRAM */
466 uintptr_t ctrl_sts_intfc_addr = get_control_status_interface();
467
468 if (!ctrl_sts_intfc_addr) {
469 printk(BIOS_ERR, "CPU crashlog control and status interface address not valid\n");
470 return;
471 }
472
473 /* If storage-off is supported, turn off the PUNIT SRAM
474 * stroage to save power. This clears crashlog records also.
475 */
476
477 if (!cpu_cl_disc_tab.header.fields.storage_off_support) {
478 printk(BIOS_INFO, "CPU crashlog storage_off not supported\n");
479 return;
480 }
481
482 cl_punit_control_interface_t punit_ctrl_intfc;
483 memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t));
484 punit_ctrl_intfc.fields.set_storage_off = 1;
485 write32p(ctrl_sts_intfc_addr, punit_ctrl_intfc.data);
486
487 if (!wait_and_check(CRASHLOG_PUNIT_STORAGE_OFF_MASK))
488 printk(BIOS_ERR, "CPU crashlog storage_off not asserted\n");
489 else
490 printk(BIOS_DEBUG, "CPU crashlog storage_off asserted\n");
491 }
492
cl_get_pmc_discovery_buf(void)493 pmc_ipc_discovery_buf_t cl_get_pmc_discovery_buf(void)
494 {
495 return discovery_buf;
496 }
497
cl_get_pmc_descriptor_table(void)498 pmc_crashlog_desc_table_t cl_get_pmc_descriptor_table(void)
499 {
500 return descriptor_table;
501 }
502
cl_get_pmc_record_size(void)503 int cl_get_pmc_record_size(void)
504 {
505 return m_pmc_crashLog_size;
506 }
507
cl_get_cpu_record_size(void)508 int cl_get_cpu_record_size(void)
509 {
510 return m_cpu_crashLog_size;
511 }
512
cl_cpu_data_present(void)513 bool cl_cpu_data_present(void)
514 {
515 return m_cpu_crashLog_present;
516 }
517
cl_pmc_data_present(void)518 bool cl_pmc_data_present(void)
519 {
520 return m_pmc_crashLog_present;
521 }
522
cpu_crashlog_support(void)523 bool cpu_crashlog_support(void)
524 {
525 return m_cpu_crashLog_support;
526 }
527
pmc_crashlog_support(void)528 bool pmc_crashlog_support(void)
529 {
530 return m_pmc_crashLog_support;
531 }
532
update_new_pmc_crashlog_size(u32 * pmc_crash_size)533 void update_new_pmc_crashlog_size(u32 *pmc_crash_size)
534 {
535 m_pmc_crashLog_size = *pmc_crash_size;
536 }
537
cl_get_cpu_discovery_table(void)538 cpu_crashlog_discovery_table_t cl_get_cpu_discovery_table(void)
539 {
540 return cpu_cl_disc_tab;
541 }
542
update_new_cpu_crashlog_size(u32 * cpu_crash_size)543 void update_new_cpu_crashlog_size(u32 *cpu_crash_size)
544 {
545 m_cpu_crashLog_size = *cpu_crash_size;
546 }
547