1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <gpio.h>
4 #include <intelblocks/pcr.h>
5 #include <soc/pcr_ids.h>
6 #include <soc/pm.h>
7
8 static const struct reset_mapping rst_map[] = {
9 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30},
10 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30},
11 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30},
12 };
13
14 static const struct reset_mapping rst_map_com2[] = {
15 { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30},
16 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30},
17 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30},
18 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30},
19 };
20
21 static const struct pad_group skl_community_com0_groups[] = {
22 INTEL_GPP(GPP_A0, GPP_A0, GPP_A23), /* GPP A */
23 INTEL_GPP(GPP_A0, GPP_B0, GPP_B23), /* GPP B */
24 };
25
26 static const struct pad_group skl_community_com1_groups[] = {
27 INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP C */
28 #if CONFIG(SKYLAKE_SOC_PCH_H)
29 INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP D */
30 INTEL_GPP(GPP_C0, GPP_E0, GPP_E12), /* GPP E */
31 INTEL_GPP(GPP_C0, GPP_F0, GPP_F23), /* GPP F */
32 INTEL_GPP(GPP_C0, GPP_G0, GPP_G23), /* GPP G */
33 INTEL_GPP(GPP_C0, GPP_H0, GPP_H23), /* GPP H */
34 #else
35 INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP D */
36 INTEL_GPP(GPP_C0, GPP_E0, GPP_E23), /* GPP E */
37 #endif
38 };
39
40 static const struct pad_group skl_community_com3_groups[] = {
41 #if CONFIG(SKYLAKE_SOC_PCH_H)
42 INTEL_GPP(GPP_I0, GPP_I0, GPP_I10), /* GPP I */
43 #else
44 INTEL_GPP(GPP_F0, GPP_F0, GPP_F23), /* GPP F */
45 INTEL_GPP(GPP_F0, GPP_G0, GPP_G7), /* GPP G */
46 #endif
47 };
48
49 static const struct pad_group skl_community_com2_groups[] = {
50 INTEL_GPP(GPD0, GPD0, GPD11), /* GPP GDP */
51 };
52
53 static const struct pad_community skl_gpio_communities[] = {
54 {
55 .port = PID_GPIOCOM0,
56 .first_pad = GPP_A0,
57 .last_pad = GPP_B23,
58 .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
59 .pad_cfg_base = PAD_CFG_BASE,
60 .host_own_reg_0 = HOSTSW_OWN_REG_0,
61 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
62 .gpi_int_en_reg_0 = GPI_INT_EN_0,
63 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
64 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
65 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
66 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
67 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
68 .name = "GPIO_COM0",
69 .acpi_path = "\\_SB.PCI0.GPIO",
70 .reset_map = rst_map,
71 .num_reset_vals = ARRAY_SIZE(rst_map),
72 .groups = skl_community_com0_groups,
73 .num_groups = ARRAY_SIZE(skl_community_com0_groups),
74 }, {
75 .port = PID_GPIOCOM1,
76 .first_pad = GPP_C0,
77 #if CONFIG(SKYLAKE_SOC_PCH_H)
78 .last_pad = GPP_H23,
79 #else
80 .last_pad = GPP_E23,
81 #endif
82 .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
83 .pad_cfg_base = PAD_CFG_BASE,
84 .host_own_reg_0 = HOSTSW_OWN_REG_0,
85 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
86 .gpi_int_en_reg_0 = GPI_INT_EN_0,
87 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
88 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
89 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
90 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
91 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
92 .name = "GPIO_COM1",
93 .acpi_path = "\\_SB.PCI0.GPIO",
94 .reset_map = rst_map,
95 .num_reset_vals = ARRAY_SIZE(rst_map),
96 .groups = skl_community_com1_groups,
97 .num_groups = ARRAY_SIZE(skl_community_com1_groups),
98 }, {
99 .port = PID_GPIOCOM3,
100 #if CONFIG(SKYLAKE_SOC_PCH_H)
101 .first_pad = GPP_I0,
102 .last_pad = GPP_I10,
103 #else
104 .first_pad = GPP_F0,
105 .last_pad = GPP_G7,
106 #endif
107 .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
108 .pad_cfg_base = PAD_CFG_BASE,
109 .host_own_reg_0 = HOSTSW_OWN_REG_0,
110 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
111 .gpi_int_en_reg_0 = GPI_INT_EN_0,
112 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
113 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
114 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
115 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
116 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
117 .name = "GPIO_COM3",
118 .acpi_path = "\\_SB.PCI0.GPIO",
119 .reset_map = rst_map,
120 .num_reset_vals = ARRAY_SIZE(rst_map),
121 .groups = skl_community_com3_groups,
122 .num_groups = ARRAY_SIZE(skl_community_com3_groups),
123 }, {
124 .port = PID_GPIOCOM2,
125 .first_pad = GPD0,
126 .last_pad = GPD11,
127 .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
128 .pad_cfg_base = PAD_CFG_BASE,
129 .host_own_reg_0 = HOSTSW_OWN_REG_0,
130 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
131 .gpi_int_en_reg_0 = GPI_INT_EN_0,
132 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
133 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
134 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
135 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
136 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
137 .name = "GPIO_COM2",
138 .acpi_path = "\\_SB.PCI0.GPIO",
139 .reset_map = rst_map_com2,
140 .num_reset_vals = ARRAY_SIZE(rst_map_com2),
141 .groups = skl_community_com2_groups,
142 .num_groups = ARRAY_SIZE(skl_community_com2_groups),
143 }
144 };
145
soc_gpio_get_community(size_t * num_communities)146 const struct pad_community *soc_gpio_get_community(size_t *num_communities)
147 {
148 *num_communities = ARRAY_SIZE(skl_gpio_communities);
149 return skl_gpio_communities;
150 }
151
soc_pmc_gpio_routes(size_t * num)152 const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
153 {
154 static const struct pmc_to_gpio_route routes[] = {
155 { GPP_A, GPP_A},
156 { GPP_B, GPP_B},
157 { GPP_C, GPP_C},
158 { GPP_D, GPP_D},
159 { GPP_E, GPP_E},
160 { GPP_F, GPP_F},
161 { GPP_G, GPP_G},
162 #if CONFIG(SKYLAKE_SOC_PCH_H)
163 { GPP_H, GPP_H},
164 { GPP_I, GPP_I},
165 #endif
166 { GPD, GPD},
167 };
168 *num = ARRAY_SIZE(routes);
169 return routes;
170 }
171
soc_gpio_pad_config_fixup(const struct pad_config * cfg,int dw_reg,uint32_t reg_val)172 uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg,
173 int dw_reg, uint32_t reg_val)
174 {
175 if (CONFIG(SKYLAKE_SOC_PCH_H))
176 return reg_val;
177 /*
178 * For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4
179 * ~ GPP_F11.
180 */
181 if (cfg->pad >= GPP_F4 && cfg->pad <= GPP_F11 && dw_reg == 1)
182 reg_val = reg_val & ~(PAD_CFG1_TOL_1V8);
183 return reg_val;
184 }
185