1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/pci_ids.h>
4 #include <device/pci_ops.h>
5 #include <fsp/api.h>
6 #include <soc/ramstage.h>
7 #include <soc/vr_config.h>
8 #include <console/console.h>
9 #include <intelblocks/cpulib.h>
10
11 /* Default values for domain configuration. */
12 static const struct vr_config default_configs[NUM_VR_DOMAINS] = {
13 [VR_SYSTEM_AGENT] = {
14 .vr_config_enable = 1,
15 .psi1threshold = VR_CFG_AMP(20),
16 .psi2threshold = VR_CFG_AMP(4),
17 .psi3threshold = VR_CFG_AMP(1),
18 .psi3enable = 1,
19 .psi4enable = 1,
20 .imon_slope = 0,
21 .imon_offset = 0,
22 .icc_max = 0,
23 .voltage_limit = 1520,
24 },
25 [VR_IA_CORE] = {
26 .vr_config_enable = 1,
27 .psi1threshold = VR_CFG_AMP(20),
28 .psi2threshold = VR_CFG_AMP(5),
29 .psi3threshold = VR_CFG_AMP(1),
30 .psi3enable = 1,
31 .psi4enable = 1,
32 .imon_slope = 0,
33 .imon_offset = 0,
34 .icc_max = 0,
35 .voltage_limit = 1520,
36 },
37 [VR_GT_UNSLICED] = {
38 .vr_config_enable = 1,
39 .psi1threshold = VR_CFG_AMP(20),
40 .psi2threshold = VR_CFG_AMP(5),
41 .psi3threshold = VR_CFG_AMP(1),
42 .psi3enable = 1,
43 .psi4enable = 1,
44 .imon_slope = 0,
45 .imon_offset = 0,
46 .icc_max = 0,
47 .voltage_limit = 1520,
48 },
49 [VR_GT_SLICED] = {
50 .vr_config_enable = 1,
51 .psi1threshold = VR_CFG_AMP(20),
52 .psi2threshold = VR_CFG_AMP(5),
53 .psi3threshold = VR_CFG_AMP(1),
54 .psi3enable = 1,
55 .psi4enable = 1,
56 .imon_slope = 0,
57 .imon_offset = 0,
58 .icc_max = 0,
59 .voltage_limit = 1520,
60 },
61 };
62
get_sku_icc_max(int domain)63 static uint16_t get_sku_icc_max(int domain)
64 {
65 const uint16_t tdp = cpu_get_power_max() / 1000;
66
67 static uint16_t mch_id = 0, igd_id = 0;
68 if (!mch_id) {
69 struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
70 mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
71 }
72 if (!igd_id) {
73 struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
74 igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
75 }
76
77 /*
78 * Iccmax table from Doc #559100 Section 7.2 DC Specifications, the
79 * Iccmax is the same among KBL-Y but KBL-U/R.
80 * Addendum for AML-Y #594883, IccMax for IA core is 28A.
81 * KBL-S #335195, KBL-H #335190, SKL-S #332687, SKL-H #332986,
82 * SKL-U/Y #332990
83 *
84 * Platform Segment SA IA GT (GT/GTx)
85 * ---------------------------------------------------------------------
86 * KBL/SKL-S (95W) quad 11.1 100 45
87 * SKL-S (80W) quad 11.1 82 45
88 * KBL/SKL-S (65W) quad 11.1 79 45
89 * SKL-S (45W) quad 11.1 70 0
90 * KBL/SKL-S (35W) quad 11.1 66 35
91 * SKL-S (25W) quad 11.1 55 35
92 *
93 * KBL/SKL-S (54W) dual 11.1 58 48
94 * KBL/SKL-S (51W) dual 11.1 45 48
95 * KBL/SKL-S (35W) dual 11.1 40 48
96 *
97 * SKL-H + OPC (65W) GT4 quad 8 74 105/24
98 * SKL-H + OPC (45W) GT4 quad 8 74 94/20
99 * SKL-H + OPC (35W) GT4 quad 8 66 94/20
100 *
101 * SKL-H (35W) GT2 dual 11.1 60 55
102 *
103 * KBL/SKL-H (45W) GT2 quad 11.1 68 55
104 * KBL-H (18W) GT2 quad 6.6 60 55
105 *
106 * SKL-U + OPC (28W) GT3 dual 5.1 32 57/19
107 * SKL-U + OPC (15W) GT3 dual 5.1 29 57/19
108 * SKL-U (15W) GT2 dual 4.5 29 31
109 *
110 * KBL-U + OPC (28W) GT3 dual 5.1 32 57/19
111 * KBL-U + OPC (15W) GT3 dual 5.1 32 57/19
112 * KBL-U (15W) GT1/2 dual 4.5 32 31
113 * KBL-U [*] (15W) GT1 quad 4.5 29 31
114 *
115 * KBL-U/R (15W) GT2 quad 6 64 31
116 *
117 * SKL/KBL-Y (6W) 4.1 24 24
118 * SKL/KBL-Y (4.5W) 4.1 24 24
119 *
120 * [*] Pentium/Celeron CPUs with HD Graphics 610
121 */
122
123 switch (mch_id) {
124 case PCI_DID_INTEL_SKL_ID_S_2: /* fallthrough */
125 case PCI_DID_INTEL_KBL_ID_S: {
126 uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 40, 48, 48);
127 if (tdp >= 54)
128 icc_max[VR_IA_CORE] = VR_CFG_AMP(58);
129 else if (tdp >= 51)
130 icc_max[VR_IA_CORE] = VR_CFG_AMP(45);
131
132 return icc_max[domain];
133 }
134 case PCI_DID_INTEL_SKL_ID_S_4: /* fallthrough */
135 case PCI_DID_INTEL_KBL_ID_DT_2: /* fallthrough */
136 case PCI_DID_INTEL_KBL_ID_DT: {
137 uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 55, 45, 45);
138 if (tdp >= 91)
139 icc_max[VR_IA_CORE] = VR_CFG_AMP(100);
140 else if (tdp >= 80)
141 icc_max[VR_IA_CORE] = VR_CFG_AMP(82);
142 else if (tdp >= 65)
143 icc_max[VR_IA_CORE] = VR_CFG_AMP(79);
144 else if (tdp >= 45) {
145 icc_max[VR_IA_CORE] = VR_CFG_AMP(70);
146 icc_max[VR_GT_SLICED] = 0;
147 icc_max[VR_GT_UNSLICED] = 0;
148 } else if (tdp >= 25) {
149 if (tdp >= 35)
150 icc_max[VR_IA_CORE] = VR_CFG_AMP(66);
151
152 icc_max[VR_GT_SLICED] = VR_CFG_AMP(35);
153 icc_max[VR_GT_UNSLICED] = VR_CFG_AMP(35);
154 }
155
156 return icc_max[domain];
157 }
158 case PCI_DID_INTEL_SKL_ID_H_4: {
159 uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 60, 94, 20);
160 if (tdp >= 45) {
161 icc_max[VR_IA_CORE] = VR_CFG_AMP(74);
162 if (tdp >= 65) {
163 icc_max[VR_GT_SLICED] = VR_CFG_AMP(105);
164 icc_max[VR_GT_UNSLICED] = VR_CFG_AMP(24);
165 }
166 }
167 return icc_max[domain];
168 }
169 case PCI_DID_INTEL_SKL_ID_H_2: /* fallthrough */
170 case PCI_DID_INTEL_SKL_ID_H_EM: /* fallthrough */
171 case PCI_DID_INTEL_KBL_ID_H: {
172 uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(6.6, 60, 55, 55);
173 if (tdp >= 35) {
174 if (tdp >= 45)
175 icc_max[VR_IA_CORE] = VR_CFG_AMP(68);
176
177 icc_max[VR_SYSTEM_AGENT] = VR_CFG_AMP(11.1);
178 }
179
180 return icc_max[domain];
181 }
182 case PCI_DID_INTEL_SKL_ID_U: {
183 uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(5.1, 29, 57, 19);
184 if (tdp >= 28)
185 icc_max[VR_IA_CORE] = VR_CFG_AMP(32);
186 else if (igd_id != PCI_DID_INTEL_SKL_GT3E_SULTM_1) {
187 const uint16_t icc_max_gt2[NUM_VR_DOMAINS] =
188 VR_CFG_ALL_DOMAINS_ICC(4.5, 29, 31, 31);
189
190 return icc_max_gt2[domain];
191 }
192 return icc_max[domain];
193 }
194 case PCI_DID_INTEL_KBL_U_R: {
195 const uint16_t icc_max[NUM_VR_DOMAINS] =
196 VR_CFG_ALL_DOMAINS_ICC(6, 64, 31, 31);
197 return icc_max[domain];
198 }
199 case PCI_DID_INTEL_SKL_ID_Y: /* fallthrough */
200 case PCI_DID_INTEL_KBL_ID_Y: {
201 uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(4.1, 24, 24, 24);
202
203 if (igd_id == PCI_DID_INTEL_AML_GT2_ULX)
204 icc_max[VR_IA_CORE] = VR_CFG_AMP(28);
205
206 return icc_max[domain];
207 }
208 case PCI_DID_INTEL_KBL_ID_U: {
209 uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(4.5, 32, 31, 31);
210
211 if (igd_id == PCI_DID_INTEL_KBL_GT1_SULTM)
212 icc_max[VR_IA_CORE] = VR_CFG_AMP(29);
213
214 else if ((igd_id == PCI_DID_INTEL_KBL_GT3E_SULTM_1) ||
215 (igd_id == PCI_DID_INTEL_KBL_GT3E_SULTM_2)) {
216 const uint16_t icc_max_gt3[NUM_VR_DOMAINS] =
217 VR_CFG_ALL_DOMAINS_ICC(5.1, 32, 57, 19);
218
219 return icc_max_gt3[domain];
220 }
221
222 return icc_max[domain];
223 }
224 default:
225 printk(BIOS_ERR, "Unknown MCH (0x%x) in %s\n", mch_id, __func__);
226 }
227 return 0;
228 }
229
get_sku_ac_dc_loadline(const int domain)230 static uint16_t get_sku_ac_dc_loadline(const int domain)
231 {
232 static uint16_t mch_id = 0, igd_id = 0;
233 if (!mch_id) {
234 struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
235 mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
236 }
237 if (!igd_id) {
238 struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
239 igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
240 }
241
242 switch (mch_id) {
243 case PCI_DID_INTEL_SKL_ID_S_2: /* fallthrough */
244 case PCI_DID_INTEL_SKL_ID_S_4: /* fallthrough */
245 case PCI_DID_INTEL_KBL_ID_S: /* fallthrough */
246 case PCI_DID_INTEL_KBL_ID_DT: /* fallthrough */
247 case PCI_DID_INTEL_KBL_ID_DT_2: {
248 /* SA Loadline is not specified */
249 const uint16_t loadline[NUM_VR_DOMAINS] =
250 VR_CFG_ALL_DOMAINS_LOADLINE(0, 2.1, 3.1, 3.1);
251 return loadline[domain];
252 }
253 case PCI_DID_INTEL_SKL_ID_H_2: /* fallthrough */
254 case PCI_DID_INTEL_SKL_ID_H_EM: /* fallthrough */
255 case PCI_DID_INTEL_SKL_ID_H_4: /* fallthrough */
256 case PCI_DID_INTEL_KBL_ID_H: {
257 const uint16_t loadline[NUM_VR_DOMAINS] =
258 VR_CFG_ALL_DOMAINS_LOADLINE(10, 1.8, 2.65, 2.65);
259
260 if (igd_id == PCI_DID_INTEL_SKL_GT4_SHALM) {
261 const uint16_t loadline_gt4[NUM_VR_DOMAINS] =
262 VR_CFG_ALL_DOMAINS_LOADLINE(6, 1.6, 1.4, 6);
263 return loadline_gt4[domain];
264 }
265
266 return loadline[domain];
267 }
268 case PCI_DID_INTEL_SKL_ID_Y: /* fallthrough */
269 case PCI_DID_INTEL_KBL_ID_Y: {
270 uint16_t loadline[NUM_VR_DOMAINS] =
271 VR_CFG_ALL_DOMAINS_LOADLINE(18, 5.9, 5.7, 5.7);
272
273 if (igd_id == PCI_DID_INTEL_AML_GT2_ULX)
274 loadline[VR_IA_CORE] = VR_CFG_MOHMS(4);
275
276 return loadline[domain];
277 }
278 case PCI_DID_INTEL_SKL_ID_U: /* fallthrough */
279 case PCI_DID_INTEL_KBL_U_R: /* fallthrough */
280 case PCI_DID_INTEL_KBL_ID_U: {
281 uint16_t loadline[NUM_VR_DOMAINS] =
282 VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 3.1, 3.1);
283
284 if ((igd_id == PCI_DID_INTEL_SKL_GT3E_SULTM_1) ||
285 (igd_id == PCI_DID_INTEL_SKL_GT3E_SULTM_2) ||
286 (igd_id == PCI_DID_INTEL_KBL_GT3E_SULTM_1) ||
287 (igd_id == PCI_DID_INTEL_KBL_GT3E_SULTM_2)) {
288 loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(2);
289 loadline[VR_GT_SLICED] = VR_CFG_MOHMS(6);
290 }
291
292 return loadline[domain];
293 }
294 default:
295 printk(BIOS_ERR, "Unknown MCH (0x%x) in %s\n", mch_id, __func__);
296 }
297 return 0;
298 }
299
fill_vr_domain_config(void * params,int domain,const struct vr_config * chip_cfg)300 void fill_vr_domain_config(void *params,
301 int domain, const struct vr_config *chip_cfg)
302 {
303 FSP_SIL_UPD *vr_params = (FSP_SIL_UPD *)params;
304 const struct vr_config *cfg;
305
306 if (domain < 0 || domain >= NUM_VR_DOMAINS)
307 return;
308
309 /* Use device tree override if requested. */
310 if (chip_cfg->vr_config_enable)
311 cfg = chip_cfg;
312 else
313 cfg = &default_configs[domain];
314
315 vr_params->VrConfigEnable[domain] = cfg->vr_config_enable;
316 vr_params->Psi1Threshold[domain] = cfg->psi1threshold;
317 vr_params->Psi2Threshold[domain] = cfg->psi2threshold;
318 vr_params->Psi3Threshold[domain] = cfg->psi3threshold;
319 vr_params->Psi3Enable[domain] = cfg->psi3enable;
320 vr_params->Psi4Enable[domain] = cfg->psi4enable;
321 vr_params->ImonSlope[domain] = cfg->imon_slope;
322 vr_params->ImonOffset[domain] = cfg->imon_offset;
323
324 /* If board provided non-zero value, use it. */
325 if (cfg->icc_max)
326 vr_params->IccMax[domain] = cfg->icc_max;
327 else
328 vr_params->IccMax[domain] = get_sku_icc_max(domain);
329 vr_params->VrVoltageLimit[domain] = cfg->voltage_limit;
330
331 if (cfg->ac_loadline)
332 vr_params->AcLoadline[domain] = cfg->ac_loadline;
333 else
334 vr_params->AcLoadline[domain] = get_sku_ac_dc_loadline(domain);
335 if (cfg->dc_loadline)
336 vr_params->DcLoadline[domain] = cfg->dc_loadline;
337 else
338 vr_params->DcLoadline[domain] = get_sku_ac_dc_loadline(domain);
339 }
340