1## SPDX-License-Identifier: GPL-2.0-only 2ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE),y) 3 4subdirs-y += romstage 5subdirs-y += ../../../cpu/intel/microcode 6subdirs-y += ../../../cpu/intel/turbo 7 8# all (bootblock, verstage, romstage, postcar, ramstage) 9all-y += gspi.c 10all-y += i2c.c 11all-y += pmutil.c 12all-y += spi.c 13all-y += uart.c 14 15bootblock-y += bootblock/bootblock.c 16bootblock-y += bootblock/pch.c 17bootblock-y += bootblock/report_platform.c 18bootblock-y += espi.c 19bootblock-y += p2sb.c 20 21romstage-y += espi.c 22romstage-y += meminit.c 23romstage-y += pcie_rp.c 24romstage-y += reset.c 25 26ramstage-y += acpi.c 27ramstage-y += chip.c 28ramstage-y += cpu.c 29ramstage-y += elog.c 30ramstage-y += espi.c 31ramstage-y += finalize.c 32ramstage-y += fsp_params.c 33ramstage-y += graphics.c 34ramstage-y += lockdown.c 35ramstage-y += lpm.c 36ramstage-y += p2sb.c 37ramstage-y += pcie_rp.c 38ramstage-y += pmc.c 39ramstage-y += reset.c 40ramstage-y += retimer.c 41ramstage-y += soundwire.c 42ramstage-y += systemagent.c 43ramstage-y += tcss.c 44ramstage-y += xhci.c 45ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog_lib.c 46 47smm-y += p2sb.c 48smm-y += pmutil.c 49smm-y += smihandler.c 50smm-y += uart.c 51smm-y += elog.c 52smm-y += xhci.c 53 54ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_PCH_H),y) 55bootblock-y += gpio_pch_h.c 56romstage-y += gpio_pch_h.c 57ramstage-y += gpio_pch_h.c 58smm-y += gpio_pch_h.c 59verstage-y += gpio_pch_h.c 60else 61bootblock-y += gpio.c 62romstage-y += gpio.c 63ramstage-y += gpio.c 64smm-y += gpio.c 65verstage-y += gpio.c 66endif 67 68CPPFLAGS_common += -I$(src)/soc/intel/tigerlake 69CPPFLAGS_common += -I$(src)/soc/intel/tigerlake/include 70 71ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_PCH_H),y) 72cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8d-01 73else 74cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8c-01 75cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8c-02 76endif 77 78endif 79