1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 /*
4 * This file is created based on Intel Tiger Lake Processor CPU Datasheet
5 * Document number: 575683
6 * Chapter number: 15
7 */
8
9 #include <device/pci.h>
10 #include <cpu/x86/mp.h>
11 #include <cpu/x86/msr.h>
12 #include <cpu/intel/smm_reloc.h>
13 #include <cpu/intel/turbo.h>
14 #include <cpu/intel/common/common.h>
15 #include <fsp/api.h>
16 #include <intelblocks/cpulib.h>
17 #include <intelblocks/mp_init.h>
18 #include <intelblocks/msr.h>
19 #include <soc/cpu.h>
20 #include <soc/msr.h>
21 #include <soc/pci_devs.h>
22 #include <soc/soc_chip.h>
23 #include <types.h>
24
cpu_soc_is_in_untrusted_mode(void)25 bool cpu_soc_is_in_untrusted_mode(void)
26 {
27 msr_t msr;
28
29 msr = rdmsr(MSR_BIOS_DONE);
30 return !!(msr.lo & ENABLE_IA_UNTRUSTED);
31 }
32
cpu_soc_bios_done(void)33 void cpu_soc_bios_done(void)
34 {
35 msr_t msr;
36
37 msr = rdmsr(MSR_BIOS_DONE);
38 msr.lo |= ENABLE_IA_UNTRUSTED;
39 wrmsr(MSR_BIOS_DONE, msr);
40 }
41
soc_fsp_load(void)42 static void soc_fsp_load(void)
43 {
44 fsps_load();
45 }
46
configure_misc(void)47 static void configure_misc(void)
48 {
49 msr_t msr;
50
51 config_t *conf = config_of_soc();
52
53 msr = rdmsr(IA32_MISC_ENABLE);
54 msr.lo |= (1 << 0); /* Fast String enable */
55 msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
56 wrmsr(IA32_MISC_ENABLE, msr);
57
58 /* Set EIST status */
59 cpu_set_eist(conf->eist_enable);
60
61 /* Disable Thermal interrupts */
62 msr.lo = 0;
63 msr.hi = 0;
64 wrmsr(IA32_THERM_INTERRUPT, msr);
65
66 /* Enable package critical interrupt only */
67 msr.lo = 1 << 4;
68 msr.hi = 0;
69 wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
70
71 /* Enable PROCHOT */
72 msr = rdmsr(MSR_POWER_CTL);
73 msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */
74 msr.lo |= (1 << 23); /* Lock it */
75 wrmsr(MSR_POWER_CTL, msr);
76 }
77
78 /* All CPUs including BSP will run the following function. */
soc_core_init(struct device * cpu)79 void soc_core_init(struct device *cpu)
80 {
81 /* Clear out pending MCEs */
82 /* TODO(adurbin): This should only be done on a cold boot. Also, some
83 * of these banks are core vs package scope. For now every CPU clears
84 * every bank. */
85 mca_configure();
86
87 enable_lapic_tpr();
88
89 /* Configure Enhanced SpeedStep and Thermal Sensors */
90 configure_misc();
91
92 enable_pm_timer_emulation();
93
94 /* Enable Direct Cache Access */
95 configure_dca_cap();
96
97 /* Set energy policy */
98 set_energy_perf_bias(ENERGY_POLICY_NORMAL);
99
100 /* Enable Turbo */
101 enable_turbo();
102 }
103
per_cpu_smm_trigger(void)104 static void per_cpu_smm_trigger(void)
105 {
106 /* Relocate the SMM handler. */
107 smm_relocate();
108 }
109
post_mp_init(void)110 static void post_mp_init(void)
111 {
112 /* Set Max Ratio */
113 cpu_set_max_ratio();
114
115 /*
116 * 1. Now that all APs have been relocated as well as the BSP let SMIs
117 * start flowing.
118 * 2. Skip enabling power button SMI and enable it after BS_CHIPS_INIT
119 * to avoid shutdown hang due to lack of init on certain IP in FSP-S.
120 */
121 global_smi_enable_no_pwrbtn();
122 }
123
124 static const struct mp_ops mp_ops = {
125 /*
126 * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP,
127 * that are set prior to ramstage.
128 * Real MTRRs programming are being done after resource allocation.
129 */
130 .pre_mp_init = soc_fsp_load,
131 .get_cpu_count = get_cpu_count,
132 .get_smm_info = smm_info,
133 .get_microcode_info = get_microcode_info,
134 .pre_mp_smm_init = smm_initialize,
135 .per_cpu_smm_trigger = per_cpu_smm_trigger,
136 .relocation_handler = smm_relocation_handler,
137 .post_mp_init = post_mp_init,
138 };
139
mp_init_cpus(struct bus * cpu_bus)140 void mp_init_cpus(struct bus *cpu_bus)
141 {
142 /* TODO: Handle mp_init_with_smm failure? */
143 mp_init_with_smm(cpu_bus, &mp_ops);
144
145 /* Thermal throttle activation offset */
146 configure_tcc_thermal_target();
147 }
148