1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 /* 4 * This file is created based on Intel Tiger Lake Processor PCH Datasheet 5 * Document number: 575857 6 * Chapter number: 4 7 */ 8 9 #include <device/mmio.h> 10 #include <intelblocks/cfg.h> 11 #include <intelpch/lockdown.h> 12 #include <soc/pm.h> 13 #include <stdint.h> 14 pmc_lock_pmsync(void)15static void pmc_lock_pmsync(void) 16 { 17 uint8_t *pmcbase; 18 uint32_t pmsyncreg; 19 20 pmcbase = pmc_mmio_regs(); 21 22 pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); 23 pmsyncreg |= PCH2CPU_TPR_CFG_LOCK; 24 write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); 25 } 26 pmc_lock_abase(void)27static void pmc_lock_abase(void) 28 { 29 uint8_t *pmcbase; 30 uint32_t reg32; 31 32 pmcbase = pmc_mmio_regs(); 33 34 reg32 = read32(pmcbase + GEN_PMCON_B); 35 reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK); 36 write32(pmcbase + GEN_PMCON_B, reg32); 37 } 38 pmc_lock_smi(void)39static void pmc_lock_smi(void) 40 { 41 uint8_t *pmcbase; 42 uint8_t reg8; 43 44 pmcbase = pmc_mmio_regs(); 45 46 reg8 = read8(pmcbase + GEN_PMCON_B); 47 reg8 |= SMI_LOCK; 48 write8(pmcbase + GEN_PMCON_B, reg8); 49 } 50 pmc_lockdown_cfg(int chipset_lockdown)51static void pmc_lockdown_cfg(int chipset_lockdown) 52 { 53 /* PMSYNC */ 54 pmc_lock_pmsync(); 55 /* Lock down ABASE and sleep stretching policy */ 56 pmc_lock_abase(); 57 58 if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) 59 pmc_lock_smi(); 60 } 61 soc_lockdown_config(int chipset_lockdown)62void soc_lockdown_config(int chipset_lockdown) 63 { 64 /* PMC lock down configuration */ 65 pmc_lockdown_cfg(chipset_lockdown); 66 } 67