1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/pci_def.h>
4 #include <intelblocks/smihandler.h>
5 #include <soc/soc_chip.h>
6 #include <soc/pci_devs.h>
7 #include <soc/pm.h>
8
smihandler_soc_disable_busmaster(pci_devfn_t dev)9 int smihandler_soc_disable_busmaster(pci_devfn_t dev)
10 {
11 /* Skip disabling PMC bus master to keep IO decode enabled */
12 if (dev == PCH_DEV_PMC)
13 return 0;
14 return 1;
15 }
16
17 const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
18 [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
19 [APM_STS_BIT] = smihandler_southbridge_apmc,
20 [PM1_STS_BIT] = smihandler_southbridge_pm1,
21 [GPE0_STS_BIT] = smihandler_southbridge_gpe0,
22 [GPIO_STS_BIT] = smihandler_southbridge_gpi,
23 [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
24 [MCSMI_STS_BIT] = smihandler_southbridge_mc,
25 #if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
26 [TCO_STS_BIT] = smihandler_southbridge_tco,
27 #endif
28 [PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
29 [MONITOR_STS_BIT] = smihandler_southbridge_monitor,
30 };
31