1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 /*
4 * This file is created based on Intel Tiger Lake Processor SA Datasheet
5 * Document number: 571131
6 * Chapter number: 3
7 */
8
9 #include <console/console.h>
10 #include <device/device.h>
11 #include <delay.h>
12 #include <device/pci.h>
13 #include <device/pci_ids.h>
14 #include <device/pci_ops.h>
15 #include <intelblocks/power_limit.h>
16 #include <intelblocks/systemagent.h>
17 #include <soc/iomap.h>
18 #include <soc/soc_chip.h>
19 #include <soc/systemagent.h>
20
21 /*
22 * SoC implementation
23 *
24 * Add all known fixed memory ranges for Host Controller/Memory
25 * controller.
26 */
soc_add_fixed_mmio_resources(struct device * dev,int * index)27 void soc_add_fixed_mmio_resources(struct device *dev, int *index)
28 {
29 static const struct sa_mmio_descriptor soc_fixed_resources[] = {
30 { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
31 "PCIEXBAR" },
32 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
33 { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
34 { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
35 { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
36 { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
37 };
38
39 sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
40 ARRAY_SIZE(soc_fixed_resources));
41
42 /* Add Vt-d resources if VT-d is enabled */
43 if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
44 return;
45
46 sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
47 ARRAY_SIZE(soc_vtd_resources));
48 }
49
50 /*
51 * SoC implementation
52 *
53 * Perform System Agent Initialization during Ramstage phase.
54 */
soc_systemagent_init(struct device * dev)55 void soc_systemagent_init(struct device *dev)
56 {
57 struct soc_power_limits_config *soc_config;
58 struct device *sa;
59 uint16_t sa_pci_id;
60 config_t *config;
61
62 /* Get System Agent PCI ID */
63 sa = pcidev_path_on_root(SA_DEVFN_ROOT);
64 sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF;
65
66 /* Enable Power Aware Interrupt Routing */
67 enable_power_aware_intr();
68
69 /* Enable BIOS Reset CPL */
70 enable_bios_reset_cpl();
71
72 /* Configure turbo power limits 1ms after reset complete bit */
73 mdelay(1);
74 config = config_of_soc();
75
76 /*
77 * Choose a power limits configuration based on the SoC SKU,
78 * differentiated here based on SA PCI ID.
79 */
80 switch (sa_pci_id) {
81 case PCI_DID_INTEL_TGL_ID_U_2_2:
82 soc_config = &config->power_limits_config[POWER_LIMITS_U_2_CORE];
83 break;
84 case PCI_DID_INTEL_TGL_ID_U_4_2:
85 soc_config = &config->power_limits_config[POWER_LIMITS_U_4_CORE];
86 break;
87 case PCI_DID_INTEL_TGL_ID_Y_2_2:
88 soc_config = &config->power_limits_config[POWER_LIMITS_Y_2_CORE];
89 break;
90 case PCI_DID_INTEL_TGL_ID_Y_4_2:
91 soc_config = &config->power_limits_config[POWER_LIMITS_Y_4_CORE];
92 break;
93 case PCI_DID_INTEL_TGL_ID_H_6_1:
94 soc_config = &config->power_limits_config[POWER_LIMITS_H_6_CORE];
95 break;
96 case PCI_DID_INTEL_TGL_ID_H_8_1:
97 soc_config = &config->power_limits_config[POWER_LIMITS_H_8_CORE];
98 break;
99 default:
100 printk(BIOS_ERR, "TGL: unknown SA ID: 0x%4x, skipping power limits "
101 "configuration\n", sa_pci_id);
102 return;
103 }
104
105 set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
106 }
107
soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)108 uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
109 {
110 switch (capid0_a_ddrsz) {
111 case 1:
112 return 8192;
113 case 2:
114 return 4096;
115 case 3:
116 return 2048;
117 default:
118 return 65536;
119 }
120 }
121