1## SPDX-License-Identifier: GPL-2.0-or-later 2 3ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y) 4 5subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx lbg 6subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx lbg 7subdirs-$(CONFIG_SOC_INTEL_SAPPHIRERAPIDS_SP) += spr ebg 8## TODO: GNR IBL codes are initially reused from EBG, will update later. 9subdirs-$(CONFIG_SOC_INTEL_GRANITERAPIDS) += gnr ebg 10 11bootblock-y += bootblock.c spi.c lpc.c pch.c report_platform.c 12romstage-y += romstage.c reset.c util.c spi.c pmutil.c memmap.c ddr.c 13romstage-y += config.c 14romstage-y += ../../../cpu/intel/car/romstage.c 15ramstage-y += uncore.c reset.c util.c lpc.c spi.c ramstage.c chip_common.c 16ramstage-y += memmap.c pch.c lockdown.c finalize.c 17ramstage-y += numa.c 18ramstage-y += config.c 19ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c pmutil.c 20ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uncore_acpi.c acpi.c 21ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c 22ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c 23ramstage-$(CONFIG_XEON_SP_HAVE_IIO_IOAPIC) += iio_ioapic.c 24smm-y += smihandler.c pmutil.c 25postcar-y += spi.c 26 27subdirs-$(CONFIG_SOC_INTEL_XEON_RAS) += ras 28 29CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include 30CPPFLAGS_common += -include $(src)/soc/intel/xeon_sp/include/soc/fsp_upd.h 31 32endif ## XEON_SP_COMMON_BASE 33