1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <arch/romstage.h>
4 #include <cbmem.h>
5 #include <console/console.h>
6 #include <device/pci_ops.h>
7 #include <device/pci_ids.h>
8 #include <cpu/x86/smm.h>
9 #include <soc/soc_util.h>
10 #include <soc/pci_devs.h>
11 #include <soc/util.h>
12 #include <security/intel/txt/txt_platform.h>
13
smm_region(uintptr_t * start,size_t * size)14 void smm_region(uintptr_t *start, size_t *size)
15 {
16 uintptr_t tseg_base = pci_read_config32(VTD_DEV(0), VTD_TSEG_BASE_CSR);
17 uintptr_t tseg_limit = pci_read_config32(VTD_DEV(0), VTD_TSEG_LIMIT_CSR);
18
19 tseg_base = ALIGN_DOWN(tseg_base, 1 * MiB);
20 tseg_limit = ALIGN_DOWN(tseg_limit, 1 * MiB);
21 /* Only the upper [31:20] bits of an address are checked against
22 * VTD_TSEG_LIMIT_CSR[31:20] which must be below or equal, so this
23 * effectively means +1MiB for the limit.
24 */
25 tseg_limit += 1 * MiB;
26
27 *start = tseg_base;
28 *size = tseg_limit - tseg_base;
29 }
30
fill_postcar_frame(struct postcar_frame * pcf)31 void fill_postcar_frame(struct postcar_frame *pcf)
32 {
33 const uintptr_t top_of_ram = cbmem_top();
34 uintptr_t cbmem_base;
35 size_t cbmem_size;
36
37 /* Try account for the CBMEM region currently used and for future use */
38 cbmem_get_region((void **)&cbmem_base, &cbmem_size);
39 printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
40 printk(BIOS_DEBUG, "cbmem base_ptr: 0x%lx, size: 0x%zx\n", cbmem_base, cbmem_size);
41 /* Assume 4MiB will be enough for future cbmem objects (FSP-S, ramstage, ...) */
42 cbmem_base -= 4 * MiB;
43 cbmem_base = ALIGN_DOWN(cbmem_base, 4 * MiB);
44
45 /* Align the top to make sure we don't use too many MTRR's */
46 cbmem_size = ALIGN_UP(top_of_ram - cbmem_base, 4 * MiB);
47
48 postcar_frame_add_mtrr(pcf, cbmem_base, cbmem_size, MTRR_TYPE_WRBACK);
49 /* Cache the TSEG region */
50 if (CONFIG(TSEG_STAGE_CACHE))
51 postcar_enable_tseg_cache(pcf);
52 }
53
54 #if !defined(__SIMPLE_DEVICE__)
txt_get_chipset_dpr(void)55 union dpr_register txt_get_chipset_dpr(void)
56 {
57 union dpr_register dpr;
58 struct device *dev = VTD_DEV(0);
59
60 dpr.raw = 0;
61
62 if (!dev) {
63 printk(BIOS_ERR, "BUS 0: Unable to find VTD PCI dev");
64 return dpr;
65 }
66
67 dpr.raw = pci_read_config32(dev, VTD_LTDPR);
68
69 dev = NULL;
70 /* Look for VTD devices on all sockets */
71 while ((dev = dev_find_device(PCI_VID_INTEL, MMAP_VTD_STACK_CFG_REG_DEVID, dev))) {
72 /* Compare the LTDPR register on all iio stacks */
73 union dpr_register test_dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) };
74 if (dpr.raw != test_dpr.raw) {
75 printk(BIOS_ERR, "LTDPR not the same on all IIO's");
76 dpr.raw = 0;
77 return dpr;
78 }
79 }
80 return dpr;
81 }
82 #endif
83