1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <assert.h>
4 #include <string.h>
5 #include <cpu/x86/lapic.h>
6 #include <cpu/x86/mp.h>
7 #include <cpu/intel/em64t101_save_state.h>
8 #include <cpu/intel/smm_reloc.h>
9 #include <console/console.h>
10 #include <device/device.h>
11 #include <device/pci_ids.h>
12 #include <smp/node.h>
13 #include <soc/msr.h>
14 #include <soc/smmrelocate.h>
15 #include <soc/pci_devs.h>
16
fill_in_relocation_params(struct smm_relocation_params * params)17 static void fill_in_relocation_params(struct smm_relocation_params *params)
18 {
19 uintptr_t tseg_base;
20 size_t tseg_size;
21
22 smm_region(&tseg_base, &tseg_size);
23
24 if (!IS_ALIGNED(tseg_base, tseg_size)) {
25 /*
26 * Note SMRR2 is supported which might support base/size combinations.
27 * For now it looks like FSP-M always uses aligned base/size, so let's
28 * not care about that.
29 */
30 printk(BIOS_WARNING,
31 "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n");
32 return;
33 }
34
35 /* SMRR has 32-bits of valid address aligned to 4KiB. */
36 if (!IS_ALIGNED(tseg_size, 4 * KiB)) {
37 printk(BIOS_WARNING,
38 "TSEG size not aligned to the minimum 4KiB! Not setting SMRR\n");
39 return;
40 }
41
42 smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size);
43
44 params->smrr_base.lo = tseg_base | MTRR_TYPE_WRBACK;
45 params->smrr_base.hi = 0;
46 params->smrr_mask.lo = ~(tseg_size - 1) | MTRR_PHYS_MASK_VALID;
47 params->smrr_mask.hi = 0;
48 }
49
setup_ied_area(struct smm_relocation_params * params)50 static void setup_ied_area(struct smm_relocation_params *params)
51 {
52 char *ied_base;
53
54 const struct ied_header ied = {
55 .signature = "INTEL RSVD",
56 .size = params->ied_size,
57 .reserved = {0},
58 };
59
60 ied_base = (void *)params->ied_base;
61
62 printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base);
63 printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size);
64
65 /* Place IED header at IEDBASE. */
66 memcpy(ied_base, &ied, sizeof(ied));
67
68 assert(params->ied_size > 1 * MiB + 32 * KiB);
69
70 /* Zero out 32KiB at IEDBASE + 1MiB */
71 memset(ied_base + 1 * MiB, 0, 32 * KiB);
72 }
73
get_smm_info(uintptr_t * perm_smbase,size_t * perm_smsize,size_t * smm_save_state_size)74 void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
75 size_t *smm_save_state_size)
76 {
77 fill_in_relocation_params(&smm_reloc_params);
78
79 smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
80
81 if (smm_reloc_params.ied_size)
82 setup_ied_area(&smm_reloc_params);
83
84 *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
85 }
86
update_save_state(int cpu,uintptr_t curr_smbase,uintptr_t staggered_smbase,struct smm_relocation_params * relo_params)87 static void update_save_state(int cpu, uintptr_t curr_smbase,
88 uintptr_t staggered_smbase,
89 struct smm_relocation_params *relo_params)
90 {
91 u32 smbase;
92 u32 iedbase;
93 em64t101_smm_state_save_area_t *save_state;
94 /*
95 * The relocated handler runs with all CPUs concurrently. Therefore
96 * stagger the entry points adjusting SMBASE downwards by save state
97 * size * CPU num.
98 */
99 smbase = staggered_smbase;
100 iedbase = relo_params->ied_base;
101
102 printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n apic_id=0x%x\n",
103 smbase, iedbase, initial_lapicid());
104
105 save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state));
106
107 save_state->smbase = smbase;
108 save_state->iedbase = iedbase;
109 }
110
111 /*
112 * The relocation work is actually performed in SMM context, but the code
113 * resides in the ramstage module. This occurs by trampolining from the default
114 * SMRAM entry point to here.
115 */
smm_relocation_handler(int cpu,uintptr_t curr_smbase,uintptr_t staggered_smbase)116 void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
117 uintptr_t staggered_smbase)
118 {
119 msr_t mtrr_cap, msr;
120 struct smm_relocation_params *relo_params = &smm_reloc_params;
121
122 printk(BIOS_DEBUG, "%s : CPU %d\n", __func__, cpu);
123
124 /* Make appropriate changes to the save state map. */
125 update_save_state(cpu, curr_smbase, staggered_smbase, relo_params);
126
127 /* Write SMRR MSRs based on indicated support. */
128 mtrr_cap = rdmsr(MTRR_CAP_MSR);
129
130 /* Set Lock bit if supported */
131 if (mtrr_cap.lo & SMRR_LOCK_SUPPORTED) {
132 msr = rdmsr(IA32_SMRR_PHYS_MASK);
133 /* Don't write the same core scope MSR if another thread has locked it,
134 otherwise system would hang. */
135 if (msr.lo & SMRR_PHYS_MASK_LOCK)
136 return;
137 relo_params->smrr_mask.lo |= SMRR_PHYS_MASK_LOCK;
138 }
139
140 if (mtrr_cap.lo & SMRR_SUPPORTED)
141 write_smrr(relo_params);
142 }
143
soc_ubox_store_resources(struct smm_pci_resource_info * slots,size_t size)144 void soc_ubox_store_resources(struct smm_pci_resource_info *slots, size_t size)
145 {
146 struct device *devices[CONFIG_MAX_SOCKET] = {0};
147 size_t devices_count = 0;
148 struct device *dev = NULL;
149
150 /*
151 * Collect all UBOX DFX devices. Depending on the actual socket count
152 * the bus numbers changed and the PCI segment group might be different.
153 * Pass all devices to SMM for platform lockdown.
154 */
155 while ((dev = dev_find_device(PCI_VID_INTEL, UBOX_DFX_DEVID, dev))) {
156 devices[devices_count++] = dev;
157 }
158
159 smm_pci_resource_store_fill_resources(slots, size, (const struct device **)devices, devices_count);
160 }
161