1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <delay.h>
4 #include <soc/rtc.h>
5 #include <soc/rtc_common.h>
6 #include <soc/mt6391.h>
7 #include <soc/pmic_wrap.h>
8 #include <types.h>
9
10 /* initialize rtc related gpio */
rtc_gpio_init(void)11 static bool rtc_gpio_init(void)
12 {
13 u16 con;
14
15 mt6391_gpio_set_pull(3, MT6391_GPIO_PULL_DISABLE,
16 MT6391_GPIO_PULL_DOWN); /* RTC_32K1V8 */
17
18 /* Export 32K clock RTC_32K2V8 */
19 rtc_read(RTC_CON, &con);
20 con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_LPEN);
21 con |= (RTC_CON_GPEN | RTC_CON_GOE);
22 con &= ~(RTC_CON_F32KOB);
23 rtc_write(RTC_CON, con);
24 return rtc_write_trigger();
25 }
26
27 /* set xosc mode */
rtc_osc_init(void)28 void rtc_osc_init(void)
29 {
30 u16 con;
31
32 /* enable 32K export */
33 rtc_gpio_init();
34
35 rtc_write(PMIC_RG_TOP_CKTST2, 0x0);
36 rtc_read(RTC_OSC32CON, &con);
37 if ((con & 0x1f) != 0x0) /* check XOSCCALI */
38 rtc_xosc_write(0x3);
39 }
40
41 /* low power detect setting */
rtc_lpd_init(void)42 static bool rtc_lpd_init(void)
43 {
44 pwrap_write_field(RTC_CON, RTC_CON_LPEN, RTC_CON_LPRST, 0);
45 if (!rtc_write_trigger())
46 return false;
47
48 pwrap_write_field(RTC_CON, RTC_CON_LPRST, 0, 0);
49 if (!rtc_write_trigger())
50 return false;
51
52 pwrap_write_field(RTC_CON, 0, RTC_CON_LPRST, 0);
53 if (!rtc_write_trigger())
54 return false;
55
56 return true;
57 }
58
59 /* rtc init check */
rtc_init(int recover)60 int rtc_init(int recover)
61 {
62 int ret;
63
64 rtc_info("recovery: %d\n", recover);
65
66 if (!rtc_writeif_unlock()) {
67 ret = -RTC_STATUS_WRITEIF_UNLOCK_FAIL;
68 goto err;
69 }
70
71 if (!rtc_gpio_init()) {
72 ret = -RTC_STATUS_GPIO_INIT_FAIL;
73 goto err;
74 }
75
76 /* Use SW to detect 32K mode instead of HW */
77 if (recover)
78 pwrap_write_field(PMIC_RG_CHRSTATUS, 0x4, 0x1, 9);
79
80 if (!rtc_xosc_write(0x3)) {
81 ret = -RTC_STATUS_OSC_SETTING_FAIL;
82 goto err;
83 }
84
85 /* In recovery mode, we need delay for register setting. */
86 if (recover)
87 mdelay(1000);
88
89 /* write powerkeys */
90 rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY);
91 rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY);
92 if (!rtc_write_trigger()) {
93 ret = -RTC_STATUS_POWERKEY_INIT_FAIL;
94 goto err;
95 }
96
97 if (recover)
98 pwrap_write_field(PMIC_RG_CHRSTATUS, 0, 0x4, 9);
99
100 if (!rtc_xosc_write(0)) {
101 ret = -RTC_STATUS_OSC_SETTING_FAIL;
102 goto err;
103 }
104
105 if (!rtc_reg_init()) {
106 ret = -RTC_STATUS_REG_INIT_FAIL;
107 goto err;
108 }
109
110 if (!rtc_lpd_init()) {
111 ret = -RTC_STATUS_LPD_INIT_FAIL;
112 goto err;
113 }
114
115 return RTC_STATUS_OK;
116 err:
117 rtc_info("init fail: ret=%d\n", ret);
118 return ret;
119 }
120
121 /* enable rtc bbpu */
rtc_bbpu_power_on(void)122 static void rtc_bbpu_power_on(void)
123 {
124 u16 bbpu;
125 int ret;
126
127 /* pull PWRBB high */
128 bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_BBPU | RTC_BBPU_PWREN;
129 rtc_write(RTC_BBPU, bbpu);
130 ret = rtc_write_trigger();
131 rtc_info("rtc_write_trigger=%d\n", ret);
132
133 /* enable DCXO to transform external 32KHz clock to 26MHz clock
134 directly sent to SoC */
135 pwrap_write_field(PMIC_RG_DCXO_FORCE_MODE1, BIT(11), 0, 0);
136 pwrap_write_field(PMIC_RG_DCXO_POR2_CON3,
137 BIT(8) | BIT(9) | BIT(10) | BIT(11), 0, 0);
138 pwrap_write_field(PMIC_RG_DCXO_CON2,
139 BIT(1) | BIT(3) | BIT(5) | BIT(6), 0, 0);
140
141 rtc_read(RTC_BBPU, &bbpu);
142 rtc_info("done BBPU=%#x\n", bbpu);
143
144 /* detect hw clock done,close RG_RTC_75K_PDN for low power setting. */
145 pwrap_write_field(PMIC_RG_TOP_CKPDN2, 0x1, 0, 14);
146 }
147
148 /* the rtc boot flow entry */
rtc_boot(void)149 void rtc_boot(void)
150 {
151 rtc_write(PMIC_RG_TOP_CKPDN, 0);
152 rtc_write(PMIC_RG_TOP_CKPDN2, 0);
153
154 rtc_boot_common();
155 rtc_bbpu_power_on();
156 }
157