1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <delay.h>
4 #include <halt.h>
5 #include <soc/rtc.h>
6 #include <soc/rtc_common.h>
7 #include <soc/mt6358.h>
8 #include <soc/pmic_wrap.h>
9 #include <timer.h>
10
11 /* initialize rtc setting of using dcxo clock */
rtc_enable_dcxo(void)12 static bool rtc_enable_dcxo(void)
13 {
14 u16 bbpu, con, osc32con, sec;
15
16 rtc_read(RTC_BBPU, &bbpu);
17 rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
18 rtc_write_trigger();
19
20 mdelay(1);
21 if (!rtc_writeif_unlock()) {
22 rtc_info("rtc_writeif_unlock() failed\n");
23 return false;
24 }
25
26 rtc_read(RTC_OSC32CON, &osc32con);
27 osc32con &= ~(RTC_EMBCK_SRC_SEL | RTC_EMBCK_SEL_MODE_MASK
28 | RTC_GPS_CKOUT_EN);
29 osc32con |= RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB
30 | RTC_EMB_K_EOSC32_MODE | RTC_EMBCK_SEL_OPTION;
31 if (!rtc_xosc_write(osc32con)) {
32 rtc_info("rtc_xosc_write() failed\n");
33 return false;
34 }
35
36 rtc_read(RTC_CON, &con);
37 rtc_read(RTC_OSC32CON, &osc32con);
38 rtc_read(RTC_AL_SEC, &sec);
39 rtc_info("con=0x%x, osc32con=0x%x, sec=0x%x\n", con, osc32con, sec);
40
41 return true;
42 }
43
44 /* initialize rtc related gpio */
rtc_gpio_init(void)45 bool rtc_gpio_init(void)
46 {
47 u16 con;
48
49 /* RTC_32K1V8 clock change from 128k div 4 source
50 * to RTC 32k source
51 */
52 pwrap_write_field(PMIC_RG_TOP_CKSEL_CON0_SET, 0x1, 0x1, 3);
53
54 /* Export 32K clock RTC_32K1V8_1 */
55 pwrap_write_field(PMIC_RG_TOP_CKPDN_CON1_CLR, 0x1, 0x1, 1);
56
57 /* Export 32K clock RTC_32K2V8 */
58 rtc_read(RTC_CON, &con);
59 con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN
60 | RTC_CON_XOSC32_LPEN);
61 con |= (RTC_CON_GPEN | RTC_CON_GOE);
62 con &= ~(RTC_CON_F32KOB);
63 rtc_write(RTC_CON, con);
64
65 return rtc_write_trigger();
66 }
67
rtc_get_frequency_meter(u16 val,u16 measure_src,u16 window_size)68 u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size)
69 {
70 u16 bbpu, osc32con;
71 u16 fqmtr_busy, fqmtr_data, fqmtr_rst, fqmtr_tcksel;
72 struct stopwatch sw;
73
74 if (val) {
75 rtc_read(RTC_BBPU, &bbpu);
76 rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
77 rtc_write_trigger();
78 rtc_read(RTC_OSC32CON, &osc32con);
79 rtc_xosc_write((osc32con & ~RTC_XOSCCALI_MASK) |
80 (val & RTC_XOSCCALI_MASK));
81 }
82
83 /* enable FQMTR clock */
84 pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1,
85 PMIC_RG_FQMTR_32K_CK_PDN_SHIFT);
86 pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1,
87 PMIC_RG_FQMTR_CK_PDN_SHIFT);
88
89 /* FQMTR reset */
90 pwrap_write_field(PMIC_RG_FQMTR_RST, 1, 1, PMIC_FQMTR_RST_SHIFT);
91 do {
92 rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data);
93 rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy);
94 } while (fqmtr_data && (fqmtr_busy & PMIC_FQMTR_CON0_BUSY));
95 rtc_read(PMIC_RG_FQMTR_RST, &fqmtr_rst);
96 /* FQMTR normal */
97 pwrap_write_field(PMIC_RG_FQMTR_RST, 0, 1, PMIC_FQMTR_RST_SHIFT);
98
99 /* set frequency meter window value (0=1X32K(fixed clock)) */
100 rtc_write(PMIC_RG_FQMTR_WINSET, window_size);
101 /* enable 26M and set test clock source */
102 rtc_write(PMIC_RG_FQMTR_CON0, PMIC_FQMTR_CON0_DCXO26M_EN | measure_src);
103 /* enable 26M -> delay 100us -> enable FQMTR */
104 udelay(100);
105 rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
106 /* enable FQMTR */
107 rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel | PMIC_FQMTR_CON0_FQMTR_EN);
108 udelay(100);
109
110 stopwatch_init_usecs_expire(&sw, FQMTR_TIMEOUT_US);
111 /* FQMTR read until ready */
112 do {
113 rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy);
114 if (stopwatch_expired(&sw)) {
115 rtc_info("get frequency time out !!\n");
116 return false;
117 }
118 } while (fqmtr_busy & PMIC_FQMTR_CON0_BUSY);
119
120 /* read data should be closed to 26M/32k = 794 */
121 rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data);
122
123 rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
124 /* disable FQMTR */
125 rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel & ~PMIC_FQMTR_CON0_FQMTR_EN);
126 /* disable FQMTR -> delay 100us -> disable 26M */
127 udelay(100);
128 /* disable 26M */
129 rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
130 rtc_write(PMIC_RG_FQMTR_CON0,
131 fqmtr_tcksel & ~PMIC_FQMTR_CON0_DCXO26M_EN);
132 rtc_info("input=0x%x, output=%d\n", val, fqmtr_data);
133
134 /* disable FQMTR clock */
135 pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1,
136 PMIC_RG_FQMTR_32K_CK_PDN_SHIFT);
137 pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1,
138 PMIC_RG_FQMTR_CK_PDN_SHIFT);
139
140 return fqmtr_data;
141 }
142
143 /* low power detect setting */
rtc_lpd_init(void)144 static bool rtc_lpd_init(void)
145 {
146 u16 con, sec;
147
148 /* set RTC_LPD_OPT */
149 rtc_read(RTC_AL_SEC, &sec);
150 sec |= RTC_LPD_OPT_F32K_CK_ALIVE;
151 rtc_write(RTC_AL_SEC, sec);
152 if (!rtc_write_trigger())
153 return false;
154
155 /* init XOSC32 to detect 32k clock stop */
156 rtc_read(RTC_CON, &con);
157 con |= RTC_CON_XOSC32_LPEN;
158 if (!rtc_lpen(con))
159 return false;
160
161 /* init EOSC32 to detect rtc low power */
162 rtc_read(RTC_CON, &con);
163 con |= RTC_CON_EOSC32_LPEN;
164 if (!rtc_lpen(con))
165 return false;
166
167 rtc_read(RTC_CON, &con);
168 con &= ~RTC_CON_XOSC32_LPEN;
169 rtc_write(RTC_CON, con);
170
171 /* set RTC_LPD_OPT */
172 rtc_read(RTC_AL_SEC, &sec);
173 sec &= ~RTC_LPD_OPT_MASK;
174 sec |= RTC_LPD_OPT_EOSC_LPD;
175 rtc_write(RTC_AL_SEC, sec);
176 if (!rtc_write_trigger())
177 return false;
178
179 return true;
180 }
181
rtc_hw_init(void)182 static bool rtc_hw_init(void)
183 {
184 u16 bbpu;
185
186 rtc_read(RTC_BBPU, &bbpu);
187 rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_INIT);
188 rtc_write_trigger();
189
190 udelay(500);
191
192 rtc_read(RTC_BBPU, &bbpu);
193 rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
194 rtc_write_trigger();
195
196 rtc_read(RTC_BBPU, &bbpu);
197 if (bbpu & RTC_BBPU_INIT) {
198 rtc_info("timeout\n");
199 return false;
200 }
201
202 return true;
203 }
204
205 /* rtc init check */
rtc_init(int recover)206 int rtc_init(int recover)
207 {
208 int ret;
209
210 rtc_info("recovery: %d\n", recover);
211
212 /* write powerkeys to enable rtc functions */
213 if (!rtc_powerkey_init()) {
214 ret = -RTC_STATUS_POWERKEY_INIT_FAIL;
215 goto err;
216 }
217
218 /* write interface unlock need to be set after powerkey match */
219 if (!rtc_writeif_unlock()) {
220 ret = -RTC_STATUS_WRITEIF_UNLOCK_FAIL;
221 goto err;
222 }
223
224 rtc_osc_init();
225
226 /* In recovery mode, we need 20ms delay for register setting. */
227 if (recover)
228 mdelay(20);
229
230 if (!rtc_gpio_init()) {
231 ret = -RTC_STATUS_GPIO_INIT_FAIL;
232 goto err;
233 }
234
235 if (!rtc_hw_init()) {
236 ret = -RTC_STATUS_HW_INIT_FAIL;
237 goto err;
238 }
239
240 if (!rtc_reg_init()) {
241 ret = -RTC_STATUS_REG_INIT_FAIL;
242 goto err;
243 }
244
245 if (!rtc_lpd_init()) {
246 ret = -RTC_STATUS_LPD_INIT_FAIL;
247 goto err;
248 }
249
250 /*
251 * After lpd init, powerkeys need to be written again to enable
252 * low power detect function.
253 */
254 if (!rtc_powerkey_init()) {
255 ret = -RTC_STATUS_POWERKEY_INIT_FAIL;
256 goto err;
257 }
258
259 return RTC_STATUS_OK;
260 err:
261 rtc_info("init fail: ret=%d\n", ret);
262 return ret;
263 }
264
265 /* enable rtc bbpu */
rtc_bbpu_power_on(void)266 void rtc_bbpu_power_on(void)
267 {
268 u16 bbpu;
269 int ret;
270
271 /* pull powerhold high, control by pmic */
272 pmic_set_power_hold(true);
273
274 /* pull PWRBB high */
275 bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_RELOAD | RTC_BBPU_PWREN;
276 rtc_write(RTC_BBPU, bbpu);
277 ret = rtc_write_trigger();
278 rtc_info("rtc_write_trigger=%d\n", ret);
279
280 rtc_read(RTC_BBPU, &bbpu);
281 rtc_info("done BBPU=%#x\n", bbpu);
282 }
283
poweroff(void)284 void poweroff(void)
285 {
286 u16 bbpu;
287
288 if (!rtc_writeif_unlock())
289 rtc_info("rtc_writeif_unlock() failed\n");
290 /* pull PWRBB low */
291 bbpu = RTC_BBPU_KEY | RTC_BBPU_RELOAD | RTC_BBPU_PWREN;
292 rtc_write(RTC_BBPU, bbpu);
293
294 pmic_set_power_hold(false);
295 halt();
296 }
297
dcxo_init(void)298 static void dcxo_init(void)
299 {
300 /* Buffer setting */
301 rtc_write(PMIC_RG_DCXO_CW15, 0xA2AA);
302 rtc_write(PMIC_RG_DCXO_CW13, 0x98E9);
303 rtc_write(PMIC_RG_DCXO_CW16, 0x9855);
304
305 /* 26M enable control */
306 /* Enable clock buffer XO_SOC, XO_CEL */
307 rtc_write(PMIC_RG_DCXO_CW00, 0x4805);
308 rtc_write(PMIC_RG_DCXO_CW11, 0x8000);
309
310 /* Load thermal coefficient */
311 rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7);
312 rtc_write(PMIC_RG_DCXO_CW21, 0x12A7);
313 rtc_write(PMIC_RG_DCXO_ELR0, 0xD004);
314 rtc_write(PMIC_RG_TOP_TMA_KEY, 0x0000);
315
316 /* Adjust OSC FPM setting */
317 rtc_write(PMIC_RG_DCXO_CW07, 0x8FFE);
318
319 /* Re-Calibrate OSC current */
320 rtc_write(PMIC_RG_DCXO_CW09, 0x008F);
321 udelay(100);
322 rtc_write(PMIC_RG_DCXO_CW09, 0x408F);
323 mdelay(5);
324 }
325
mt6358_dcxo_disable_unused(void)326 void mt6358_dcxo_disable_unused(void)
327 {
328 /* Disable clock buffer XO_CEL */
329 rtc_write(PMIC_RG_DCXO_CW00_CLR, 0x0800);
330 /* Mask bblpm request and switch off bblpm mode */
331 rtc_write(PMIC_RG_DCXO_CW23, 0x0052);
332 }
333
334 /* the rtc boot flow entry */
rtc_boot(void)335 void rtc_boot(void)
336 {
337 /* dcxo clock init settings */
338 dcxo_init();
339
340 /* dcxo 32k init settings */
341 pwrap_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0);
342 pwrap_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0);
343
344 /* use dcxo 32K clock */
345 if (!rtc_enable_dcxo())
346 rtc_info("rtc_enable_dcxo() failed\n");
347
348 rtc_boot_common();
349 rtc_bbpu_power_on();
350 }
351