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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 /*
4  * This file is created based on MT8186 Functional Specification
5  * Chapter number: 5.13
6  */
7 
8 #include <delay.h>
9 #include <soc/rtc.h>
10 #include <soc/rtc_common.h>
11 #include <soc/mt6366.h>
12 #include <soc/pmic_wrap.h>
13 #include <timer.h>
14 
15 #define MT8186_RTC_DXCO_CAPID 0xE0
16 
17 /* Initialize RTC setting of using DCXO clock */
rtc_enable_dcxo(void)18 static bool rtc_enable_dcxo(void)
19 {
20 	u16 bbpu, con, osc32con, sec;
21 
22 	rtc_read(RTC_BBPU, &bbpu);
23 	rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
24 
25 	if (!rtc_write_trigger()) {
26 		rtc_info("rtc_write_trigger() failed\n");
27 		return false;
28 	}
29 
30 	mdelay(1);
31 	if (!rtc_writeif_unlock()) {
32 		rtc_info("rtc_writeif_unlock() failed\n");
33 		return false;
34 	}
35 
36 	rtc_read(RTC_OSC32CON, &osc32con);
37 	osc32con &= ~(RTC_EMBCK_SRC_SEL | RTC_EMBCK_SEL_MODE_MASK
38 		      | RTC_GPS_CKOUT_EN);
39 	osc32con |= RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB
40 		    | RTC_EMB_K_EOSC32_MODE | RTC_EMBCK_SEL_OPTION;
41 	if (!rtc_xosc_write(osc32con)) {
42 		rtc_info("rtc_xosc_write() failed\n");
43 		return false;
44 	}
45 
46 	rtc_read(RTC_CON, &con);
47 	rtc_read(RTC_OSC32CON, &osc32con);
48 	rtc_read(RTC_AL_SEC, &sec);
49 	rtc_info("con = %#x, osc32con = %#x, sec = %#x\n", con, osc32con, sec);
50 
51 	return true;
52 }
53 
54 /* Initialize RTC related gpio */
rtc_gpio_init(void)55 bool rtc_gpio_init(void)
56 {
57 	u16 con;
58 
59 	/* RTC_32K1V8 clock change from 128k div 4 source to RTC 32k source */
60 	pwrap_write_field(PMIC_RG_TOP_CKSEL_CON0_SET, 0x1, 0x1, 3);
61 
62 	/* Export 32K clock RTC_32K1V8_1 */
63 	pwrap_write_field(PMIC_RG_TOP_CKPDN_CON1_CLR, 0x1, 0x1, 1);
64 
65 	/* Export 32K clock RTC_32K2V8 */
66 	rtc_read(RTC_CON, &con);
67 	con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN
68 		| RTC_CON_XOSC32_LPEN);
69 	con |= (RTC_CON_GPEN | RTC_CON_GOE);
70 	con &= ~RTC_CON_F32KOB;
71 	rtc_write(RTC_CON, con);
72 
73 	return rtc_write_trigger();
74 }
75 
rtc_get_frequency_meter(u16 val,u16 measure_src,u16 window_size)76 u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size)
77 {
78 	u16 bbpu, osc32con;
79 	u16 fqmtr_busy, fqmtr_data, fqmtr_rst, fqmtr_tcksel;
80 	struct stopwatch sw;
81 
82 	rtc_read(RTC_BBPU, &bbpu);
83 	rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
84 	if (!rtc_write_trigger()) {
85 		rtc_info("rtc_write_trigger() failed\n");
86 		return false;
87 	}
88 
89 	rtc_read(RTC_OSC32CON, &osc32con);
90 	if (!rtc_xosc_write((osc32con & ~RTC_XOSCCALI_MASK) |
91 			    (val & RTC_XOSCCALI_MASK))) {
92 		rtc_info("rtc_xosc_write() failed\n");
93 		return false;
94 	}
95 
96 	/* Enable FQMTR clock */
97 	pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1,
98 			  PMIC_RG_FQMTR_32K_CK_PDN_SHIFT);
99 	pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1,
100 			  PMIC_RG_FQMTR_CK_PDN_SHIFT);
101 
102 	/* FQMTR reset */
103 	pwrap_write_field(PMIC_RG_FQMTR_RST, 1, 1, PMIC_FQMTR_RST_SHIFT);
104 	do {
105 		rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data);
106 		rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy);
107 	} while (fqmtr_data && (fqmtr_busy & PMIC_FQMTR_CON0_BUSY));
108 	rtc_read(PMIC_RG_FQMTR_RST, &fqmtr_rst);
109 	/* FQMTR normal */
110 	pwrap_write_field(PMIC_RG_FQMTR_RST, 0, 1, PMIC_FQMTR_RST_SHIFT);
111 
112 	/* Set frequency meter window value (0=1X32K(fixed clock)) */
113 	rtc_write(PMIC_RG_FQMTR_WINSET, window_size);
114 	/* Enable 26M and set test clock source */
115 	rtc_write(PMIC_RG_FQMTR_CON0, PMIC_FQMTR_CON0_DCXO26M_EN | measure_src);
116 	/* Enable 26M -> delay 100us -> enable FQMTR */
117 	udelay(100);
118 	rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
119 	/* Enable FQMTR */
120 	rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel | PMIC_FQMTR_CON0_FQMTR_EN);
121 	udelay(100);
122 
123 	stopwatch_init_usecs_expire(&sw, FQMTR_TIMEOUT_US);
124 	/* FQMTR read until ready */
125 	if (!wait_us(FQMTR_TIMEOUT_US,
126 		     rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy) == 0 &&
127 		     !(fqmtr_busy & PMIC_FQMTR_CON0_BUSY))) {
128 		rtc_info("get frequency time out: %#x\n", fqmtr_busy);
129 		return false;
130 	}
131 
132 	/* Read data should be closed to 26M/32k = 794 */
133 	rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data);
134 
135 	rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
136 	/* Disable FQMTR */
137 	rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel & ~PMIC_FQMTR_CON0_FQMTR_EN);
138 	/* Disable FQMTR -> delay 100us -> disable 26M */
139 	udelay(100);
140 	/* Disable 26M */
141 	rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
142 	rtc_write(PMIC_RG_FQMTR_CON0,
143 		  fqmtr_tcksel & ~PMIC_FQMTR_CON0_DCXO26M_EN);
144 	rtc_info("input = %#x, output = %#x\n", val, fqmtr_data);
145 
146 	/* Disable FQMTR clock */
147 	pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1,
148 			  PMIC_RG_FQMTR_32K_CK_PDN_SHIFT);
149 	pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1,
150 			  PMIC_RG_FQMTR_CK_PDN_SHIFT);
151 
152 	return fqmtr_data;
153 }
154 
155 /* Low power detect setting */
rtc_lpd_init(void)156 static bool rtc_lpd_init(void)
157 {
158 	u16 con, sec;
159 
160 	/* Set RTC_LPD_OPT */
161 	rtc_read(RTC_AL_SEC, &sec);
162 	sec |= RTC_LPD_OPT_F32K_CK_ALIVE;
163 	rtc_write(RTC_AL_SEC, sec);
164 	if (!rtc_write_trigger()) {
165 		rtc_info("rtc_write_trigger() failed\n");
166 		return false;
167 	}
168 
169 	/* Initialize XOSC32 to detect 32k clock stop */
170 	rtc_read(RTC_CON, &con);
171 	con |= RTC_CON_XOSC32_LPEN;
172 	if (!rtc_lpen(con))
173 		return false;
174 
175 	/* Initialize EOSC32 to detect RTC low power */
176 	rtc_read(RTC_CON, &con);
177 	con |= RTC_CON_EOSC32_LPEN;
178 	if (!rtc_lpen(con))
179 		return false;
180 
181 	rtc_read(RTC_CON, &con);
182 	con &= ~RTC_CON_XOSC32_LPEN;
183 	rtc_write(RTC_CON, con);
184 
185 	/* Set RTC_LPD_OPT */
186 	rtc_read(RTC_AL_SEC, &sec);
187 	sec &= ~RTC_LPD_OPT_MASK;
188 	sec |= RTC_LPD_OPT_EOSC_LPD;
189 	rtc_write(RTC_AL_SEC, sec);
190 	if (!rtc_write_trigger()) {
191 		rtc_info("rtc_write_trigger() failed\n");
192 		return false;
193 	}
194 
195 	return true;
196 }
197 
rtc_hw_init(void)198 static bool rtc_hw_init(void)
199 {
200 	u16 bbpu;
201 
202 	rtc_read(RTC_BBPU, &bbpu);
203 	rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_INIT);
204 	if (!rtc_write_trigger()) {
205 		rtc_info("rtc_write_trigger() failed\n");
206 		return false;
207 	}
208 
209 	udelay(500);
210 
211 	rtc_read(RTC_BBPU, &bbpu);
212 	rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
213 	if (!rtc_write_trigger()) {
214 		rtc_info("rtc_write_trigger() failed\n");
215 		return false;
216 	}
217 
218 	rtc_read(RTC_BBPU, &bbpu);
219 	if (bbpu & RTC_BBPU_INIT) {
220 		rtc_info("timeout\n");
221 		return false;
222 	}
223 
224 	return true;
225 }
226 
mt6366_dcxo_disable_unused(void)227 static void mt6366_dcxo_disable_unused(void)
228 {
229 	/* Disable clock buffer XO_CEL */
230 	rtc_write(PMIC_RG_DCXO_CW00_CLR, 0x0800);
231 	/* Mask bblpm request and switch off bblpm mode */
232 	rtc_write(PMIC_RG_DCXO_CW23, 0x0052);
233 }
234 
rtc_set_capid(u16 capid)235 static void rtc_set_capid(u16 capid)
236 {
237 	u16 read_capid;
238 
239 	rtc_write(PMIC_RG_DCXO_CW03, 0xFF00 | capid);
240 
241 	rtc_read(PMIC_RG_DCXO_CW03, &read_capid);
242 	rtc_info("read back capid: %#x\n", read_capid & 0xFF);
243 }
244 
245 /* Check RTC Initialization */
rtc_init(int recover)246 int rtc_init(int recover)
247 {
248 	int ret;
249 
250 	rtc_info("recovery: %d\n", recover);
251 
252 	/* Write powerkeys to enable RTC functions */
253 	if (!rtc_powerkey_init()) {
254 		ret = -RTC_STATUS_POWERKEY_INIT_FAIL;
255 		goto err;
256 	}
257 
258 	/* Write interface unlock need to be set after powerkey match */
259 	if (!rtc_writeif_unlock()) {
260 		ret = -RTC_STATUS_WRITEIF_UNLOCK_FAIL;
261 		goto err;
262 	}
263 
264 	rtc_osc_init();
265 
266 	/* In recovery mode, we need 20ms delay for register setting. */
267 	if (recover)
268 		mdelay(20);
269 
270 	if (!rtc_gpio_init()) {
271 		ret = -RTC_STATUS_GPIO_INIT_FAIL;
272 		goto err;
273 	}
274 
275 	if (!rtc_hw_init()) {
276 		ret = -RTC_STATUS_HW_INIT_FAIL;
277 		goto err;
278 	}
279 
280 	if (!rtc_reg_init()) {
281 		ret = -RTC_STATUS_REG_INIT_FAIL;
282 		goto err;
283 	}
284 
285 	if (!rtc_lpd_init()) {
286 		ret = -RTC_STATUS_LPD_INIT_FAIL;
287 		goto err;
288 	}
289 
290 	/*
291 	 * After lpd init, powerkeys need to be written again to enable
292 	 * low power detect function.
293 	 */
294 	if (!rtc_powerkey_init()) {
295 		ret = -RTC_STATUS_POWERKEY_INIT_FAIL;
296 		goto err;
297 	}
298 
299 	return RTC_STATUS_OK;
300 err:
301 	rtc_info("init failed: ret = %d\n", ret);
302 	return ret;
303 }
304 
305 /* Enable RTC bbpu */
rtc_bbpu_power_on(void)306 void rtc_bbpu_power_on(void)
307 {
308 	u16 bbpu;
309 	int ret;
310 
311 	/* Pull powerhold high, control by pmic */
312 	mt6366_set_power_hold(true);
313 
314 	/* Pull PWRBB high */
315 	bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_RELOAD | RTC_BBPU_PWREN;
316 	rtc_write(RTC_BBPU, bbpu);
317 	ret = rtc_write_trigger();
318 	rtc_info("rtc_write_trigger = %d\n", ret);
319 
320 	rtc_read(RTC_BBPU, &bbpu);
321 	rtc_info("done BBPU = %#x\n", bbpu);
322 }
323 
dcxo_init(void)324 static void dcxo_init(void)
325 {
326 	/* Buffer setting */
327 	rtc_write(PMIC_RG_DCXO_CW15, 0xA2AA);
328 	rtc_write(PMIC_RG_DCXO_CW13, 0x98E9);
329 	rtc_write(PMIC_RG_DCXO_CW16, 0x9855);
330 
331 	/* 26M enable control */
332 	/* Enable clock buffer XO_SOC, XO_CEL */
333 	rtc_write(PMIC_RG_DCXO_CW00, 0x4805);
334 	rtc_write(PMIC_RG_DCXO_CW11, 0x8000);
335 
336 	/* Load thermal coefficient */
337 	rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7);
338 	rtc_write(PMIC_RG_DCXO_CW21, 0x12A7);
339 	rtc_write(PMIC_RG_DCXO_ELR0, 0xD004);
340 	rtc_write(PMIC_RG_TOP_TMA_KEY, 0x0000);
341 
342 	/* Adjust OSC FPM setting */
343 	rtc_write(PMIC_RG_DCXO_CW07, 0x8FFE);
344 
345 	/* Re-calibrate OSC current */
346 	rtc_write(PMIC_RG_DCXO_CW09, 0x008F);
347 	udelay(100);
348 	rtc_write(PMIC_RG_DCXO_CW09, 0x408F);
349 	mdelay(5);
350 
351 	rtc_set_capid(MT8186_RTC_DXCO_CAPID);
352 
353 	mt6366_dcxo_disable_unused();
354 }
355 
356 /* Initialize rtc boot flow */
rtc_boot(void)357 void rtc_boot(void)
358 {
359 	/* DCXO clock initialized settings */
360 	dcxo_init();
361 
362 	/* DCXO 32k initialized settings */
363 	pwrap_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0);
364 	pwrap_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0);
365 
366 	/* Use DCXO 32K clock */
367 	if (!rtc_enable_dcxo())
368 		rtc_info("rtc_enable_dcxo() failed\n");
369 
370 	rtc_boot_common();
371 	rtc_bbpu_power_on();
372 }
373