1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/mmio.h>
4 #include <soc/iocfg.h>
5 #include <soc/pll.h>
6 #include <soc/pmif_spmi.h>
7
8 /* IOCFG_BM, DRV_CFG2 */
9 DEFINE_BITFIELD(SPMI_SCL, 5, 3)
10 DEFINE_BITFIELD(SPMI_SDA, 8, 6)
11
12 /* TOPRGU, WDT_SWSYSRST2 */
13 DEFINE_BIT(SPMI_MST_RST, 4)
14 DEFINE_BITFIELD(UNLOCK_KEY, 31, 24)
15
16 /* TOPCKGEN, CLK_CFG_15 */
17 DEFINE_BITFIELD(CLK_SPMI_MST_SEL, 10, 8)
18 DEFINE_BIT(CLK_SPMI_MST_INT, 12)
19 DEFINE_BIT(PDN_SPMI_MST, 15)
20
21 /* TOPCKGEN, CLK_CFG_UPDATE2 */
22 DEFINE_BIT(SPMI_MST_CK_UPDATE, 30)
23
24 const struct spmi_device spmi_dev[] = {
25 {
26 .slvid = SPMI_SLAVE_6,
27 .type = BUCK_CPU,
28 .type_id = BUCK_CPU_ID,
29 },
30 {
31 .slvid = SPMI_SLAVE_7,
32 .type = BUCK_GPU,
33 .type_id = BUCK_GPU_ID,
34 },
35 };
36
37 const size_t spmi_dev_cnt = ARRAY_SIZE(spmi_dev);
38
spmi_config_master(void)39 int spmi_config_master(void)
40 {
41 /* Software reset */
42 SET32_BITFIELDS(&mtk_rug->wdt_swsysrst2, SPMI_MST_RST, 1, UNLOCK_KEY, 0x85);
43
44 SET32_BITFIELDS(&mtk_topckgen->clk_cfg_15_clr,
45 CLK_SPMI_MST_SEL, 0x7,
46 CLK_SPMI_MST_INT, 1,
47 PDN_SPMI_MST, 1);
48 SET32_BITFIELDS(&mtk_topckgen->clk_cfg_update2, SPMI_MST_CK_UPDATE, 1);
49
50 /* Software reset */
51 SET32_BITFIELDS(&mtk_rug->wdt_swsysrst2, SPMI_MST_RST, 0, UNLOCK_KEY, 0x85);
52
53 /* Enable SPMI */
54 write32(&mtk_spmi_mst->mst_req_en, 1);
55
56 return 0;
57 }
58
pmif_spmi_config(struct pmif * arb,int mstid)59 void pmif_spmi_config(struct pmif *arb, int mstid)
60 {
61 u32 cmd_per;
62
63 /* Clear all cmd permission for per channel */
64 write32(&arb->mtk_pmif->inf_cmd_per_0, 0);
65 write32(&arb->mtk_pmif->inf_cmd_per_1, 0);
66 write32(&arb->mtk_pmif->inf_cmd_per_2, 0);
67 write32(&arb->mtk_pmif->inf_cmd_per_3, 0);
68
69 /* Enable if we need cmd 0~3 permission for per channel */
70 cmd_per = PMIF_CMD_PER_3 << 28 | PMIF_CMD_PER_3 << 24 |
71 PMIF_CMD_PER_3 << 20 | PMIF_CMD_PER_3 << 16 |
72 PMIF_CMD_PER_3 << 8 | PMIF_CMD_PER_3 << 4 |
73 PMIF_CMD_PER_1_3 << 0;
74 write32(&arb->mtk_pmif->inf_cmd_per_0, cmd_per);
75
76 cmd_per = PMIF_CMD_PER_3 << 4;
77 write32(&arb->mtk_pmif->inf_cmd_per_1, cmd_per);
78 }
79
pmif_spmi_iocfg(void)80 void pmif_spmi_iocfg(void)
81 {
82 SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg2, SPMI_SCL, 0x2, SPMI_SDA, 0x2);
83 }
84