1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
2
3 #include <device/mmio.h>
4 #include <soc/iocfg.h>
5 #include <soc/pll.h>
6 #include <soc/pmif_spmi.h>
7
8 /* IOCFG_BM, DRV_CFG2 */
9 DEFINE_BITFIELD(SPMI_SCL, 8, 6)
10 DEFINE_BITFIELD(SPMI_SDA, 11, 9)
11 DEFINE_BIT(SPMI_SCL_IN, 20)
12 DEFINE_BIT(SPMI_SDA_IN, 21)
13 DEFINE_BIT(SPMI_SCL_PU, 21)
14 DEFINE_BIT(SPMI_SDA_PD, 22)
15 DEFINE_BIT(SPMI_SCL_SMT, 25)
16 DEFINE_BIT(SPMI_SDA_SMT, 26)
17 DEFINE_BITFIELD(SPMI_TD, 11, 8)
18 DEFINE_BITFIELD(SPMI_RD, 23, 22)
19 DEFINE_BITFIELD(SPMI_DRI, 5, 0)
20
21 /* TOPRGU, WDT_SWSYSRST2 */
22 DEFINE_BIT(SPMI_MST_RST, 23)
23 DEFINE_BITFIELD(UNLOCK_KEY, 31, 24)
24
25 /* TOPCKGEN, CLK_CFG_17 */
26 DEFINE_BITFIELD(CLK_SPMI_MST_SEL, 10, 8)
27 DEFINE_BIT(CLK_SPMI_MST_INT, 12)
28 DEFINE_BIT(PDN_SPMI_MST, 15)
29
30 /* TOPCKGEN, CLK_CFG_UPDATE2 */
31 DEFINE_BIT(SPMI_MST_CK_UPDATE, 5)
32
33 const struct spmi_device spmi_dev[] = {
34 {
35 .slvid = SPMI_SLAVE_6,
36 .type = BUCK_CPU,
37 .type_id = BUCK_CPU_ID,
38 },
39 {
40 .slvid = SPMI_SLAVE_7,
41 .type = BUCK_GPU,
42 .type_id = BUCK_GPU_ID,
43 },
44 };
45
46 const size_t spmi_dev_cnt = ARRAY_SIZE(spmi_dev);
47
spmi_config_master(void)48 int spmi_config_master(void)
49 {
50 /* Software reset */
51 SET32_BITFIELDS(&mtk_rug->wdt_swsysrst2, SPMI_MST_RST, 1, UNLOCK_KEY, 0x88);
52
53 SET32_BITFIELDS(&mtk_topckgen->clk_cfg_17,
54 CLK_SPMI_MST_SEL, 0x3,
55 CLK_SPMI_MST_INT, 0,
56 PDN_SPMI_MST, 0);
57 SET32_BITFIELDS(&mtk_topckgen->clk_cfg_update2, SPMI_MST_CK_UPDATE, 1);
58
59 /* Software reset */
60 SET32_BITFIELDS(&mtk_rug->wdt_swsysrst2, SPMI_MST_RST, 0, UNLOCK_KEY, 0x88);
61
62 /* Enable SPMI */
63 write32(&mtk_spmi_mst->mst_req_en, 1);
64 write32(&mtk_spmi_mst->rcs_ctrl, 0x15);
65
66 return 0;
67 }
68
pmif_spmi_config(struct pmif * arb,int mstid)69 void pmif_spmi_config(struct pmif *arb, int mstid)
70 {
71 u32 cmd_per;
72
73 /* Clear all cmd permission for per channel */
74 write32(&arb->mtk_pmif->inf_cmd_per_0, 0);
75 write32(&arb->mtk_pmif->inf_cmd_per_1, 0);
76 write32(&arb->mtk_pmif->inf_cmd_per_2, 0);
77 write32(&arb->mtk_pmif->inf_cmd_per_3, 0);
78
79 /* Enable if we need cmd 0~3 permission for per channel */
80 cmd_per = PMIF_CMD_PER_3 << 28 | PMIF_CMD_PER_3 << 24 |
81 PMIF_CMD_PER_3 << 20 | PMIF_CMD_PER_3 << 16 |
82 PMIF_CMD_PER_3 << 8 | PMIF_CMD_PER_3 << 4 |
83 PMIF_CMD_PER_1_3 << 0;
84 write32(&arb->mtk_pmif->inf_cmd_per_0, cmd_per);
85
86 cmd_per = PMIF_CMD_PER_3 << 4;
87 write32(&arb->mtk_pmif->inf_cmd_per_1, cmd_per);
88 }
89
pmif_spmi_iocfg(void)90 void pmif_spmi_iocfg(void)
91 {
92 SET32_BITFIELDS(&mtk_iocfg_bm->eh_cfg_clr, SPMI_SCL, 0x7, SPMI_SDA, 0x7);
93 SET32_BITFIELDS(&mtk_iocfg_bm->ies_cfg1_clr, SPMI_SCL_IN, 0x1);
94 SET32_BITFIELDS(&mtk_iocfg_bm->ies_cfg1_set, SPMI_SDA_IN, 0x1);
95 SET32_BITFIELDS(&mtk_iocfg_bm->pu_cfg1_clr, SPMI_SCL_PU, 0x1,
96 SPMI_SDA_PD, 0x1);
97 SET32_BITFIELDS(&mtk_iocfg_bm->pd_cfg1_clr, SPMI_SCL_PU, 0x1,
98 SPMI_SDA_PD, 0x1);
99 SET32_BITFIELDS(&mtk_iocfg_bm->smt_cfg0_set, SPMI_SCL_SMT, 0x1,
100 SPMI_SDA_SMT, 0x1);
101 SET32_BITFIELDS(&mtk_iocfg_bm->tdsel_cfg1_clr, SPMI_TD, 0xF);
102 SET32_BITFIELDS(&mtk_iocfg_bm->rdsel_cfg0_clr, SPMI_RD, 0x3);
103 SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg3_clr, SPMI_DRI, 0x2D);
104 SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg3_set, SPMI_DRI, 0x12);
105 }
106