1/* SPDX-License-Identifier: GPL-2.0-only */ 2 3#include <memlayout.h> 4 5#include <arch/header.ld> 6 7/* 8 * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself, 9 * so the bootblock loading address must be placed after that. After the 10 * handoff that area may be reclaimed for other uses, e.g. CBFS cache. 11 */ 12 13SECTIONS 14{ 15 SRAM_START(0x40000000) 16 TTB(0x40000000, 16K + 32) 17 PRERAM_CBMEM_CONSOLE(0x40004020, 6K - 32) 18 FMAP_CACHE(0x40005800, 2K) 19 CBFS_MCACHE(0x40006000, 8K) 20 PRERAM_CBFS_CACHE(0x40008000, 6K) 21 VBOOT2_WORK(0x40009800, 12K) 22 TPM_LOG(0x4000D800, 2K) 23 STACK(0x4000E000, 8K) 24 BOOTBLOCK(0x40010000, 32K) 25 VERSTAGE(0x40018000, 70K) 26 ROMSTAGE(0x40029800, 89K) 27 TIMESTAMP(0x4003FC00, 1K) 28 SRAM_END(0x40040000) 29 30 DRAM_START(0x80000000) 31 POSTRAM_CBFS_CACHE(0x80100000, 1M) 32 RAMSTAGE(0x80200000, 2M) 33 DMA_COHERENT(0x90000000, 2M) 34} 35