1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/mmio.h>
4 #include <console/console.h>
5 #include <soc/addressmap.h>
6 #include <soc/clock.h>
7 #include <soc/clk_rst.h>
8 #include <soc/ccplex.h>
9 #include <soc/cpu.h>
10 #include <soc/flow.h>
11 #include <soc/mc.h>
12 #include <soc/pmc.h>
13 #include <soc/power.h>
14 #include <soc/romstage.h>
15 #include <timer.h>
16
17 #define PMC_REGS (void *)(uintptr_t)(TEGRA_PMC_BASE)
18
enable_cpu_clocks(void)19 static void enable_cpu_clocks(void)
20 {
21 clock_enable(CLK_ENB_CPU, 0, 0, SET_CLK_ENB_CPUG_ENABLE |
22 SET_CLK_ENB_CPULP_ENABLE, 0, 0, 0);
23 }
24
enable_cpu_power_partitions(void)25 static void enable_cpu_power_partitions(void)
26 {
27 /* Bring up fast cluster, non-CPU, CPU0, CPU1, CPU2 and CPU3 parts. */
28 power_ungate_partition(POWER_PARTID_CRAIL);
29 power_ungate_partition(POWER_PARTID_C0NC);
30 power_ungate_partition(POWER_PARTID_CE0);
31
32 if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE)) {
33 /*
34 * Deassert reset signal of all the secondary CPUs.
35 * PMC and flow controller will take over the power sequence
36 * controller in the ATF.
37 */
38 uint32_t reg = CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_DBG1 |
39 CRC_RST_CPUG_CLR_CORE1 | CRC_RST_CPUG_CLR_CX1 |
40 CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_DBG2 |
41 CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CX2 |
42 CRC_RST_CPUG_CLR_CPU3 | CRC_RST_CPUG_CLR_DBG3 |
43 CRC_RST_CPUG_CLR_CORE3 | CRC_RST_CPUG_CLR_CX3;
44 write32(CLK_RST_REG(rst_cpug_cmplx_clr), reg);
45 }
46 }
47
request_ram_repair(void)48 static void request_ram_repair(void)
49 {
50 struct flow_ctlr * const flow = (void *)(uintptr_t)TEGRA_FLOW_BASE;
51 const uint32_t req = 1 << 0;
52 const uint32_t sts = 1 << 1;
53 uint32_t reg;
54 struct stopwatch sw;
55
56 printk(BIOS_DEBUG, "Requesting RAM repair.\n");
57
58 stopwatch_init(&sw);
59
60 /* Perform RAM repair */
61 reg = read32(&flow->ram_repair);
62 reg |= req;
63 write32(&flow->ram_repair, reg);
64 while ((read32(&flow->ram_repair) & sts) != sts)
65 ;
66
67 printk(BIOS_DEBUG, "RAM repair complete in %lld usecs.\n",
68 stopwatch_duration_usecs(&sw));
69 }
70
set_cpu_ack_width(uint32_t val)71 static void set_cpu_ack_width(uint32_t val)
72 {
73 uint32_t reg;
74
75 reg = read32(CLK_RST_REG(cpu_softrst_ctrl2));
76 reg &= ~CAR2PMC_CPU_ACK_WIDTH_MASK;
77 reg |= val;
78 write32(CLK_RST_REG(cpu_softrst_ctrl2), reg);
79 }
80
ccplex_cpu_prepare(void)81 void ccplex_cpu_prepare(void)
82 {
83 enable_cpu_clocks();
84
85 /*
86 * The POR value of CAR2PMC_CPU_ACK_WIDTH is 0x200.
87 * The recommended value is 0.
88 */
89 set_cpu_ack_width(0);
90
91 enable_cpu_power_partitions();
92
93 mainboard_configure_pmc();
94 mainboard_enable_vdd_cpu();
95
96 request_ram_repair();
97 }
98
start_common_clocks(void)99 static void start_common_clocks(void)
100 {
101 /* Clear fast CPU partition reset. */
102 write32(CLK_RST_REG(rst_cpug_cmplx_clr), CRC_RST_CPUG_CLR_NONCPU);
103
104 /* Clear reset of L2 and CoreSight components. */
105 write32(CLK_RST_REG(rst_cpug_cmplx_clr),
106 CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG);
107 }
108
ccplex_cpu_start(void * entry_addr)109 void ccplex_cpu_start(void *entry_addr)
110 {
111 /* Enable common clocks for the shared resources between the cores. */
112 start_common_clocks();
113
114 start_cpu(0, entry_addr);
115 }
116