1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <bootmem.h>
4 #include <bootmode.h>
5 #include <bootstate.h>
6 #include <console/console.h>
7 #include <device/device.h>
8 #include <soc/nvidia/tegra/dc.h>
9 #include <soc/addressmap.h>
10 #include <soc/clock.h>
11 #include <soc/cpu.h>
12 #include <soc/mc.h>
13 #include <soc/nvidia/tegra/apbmisc.h>
14 #include <soc/sdram.h>
15 #include <soc/sdram_configs.h>
16
17 #include "chip.h"
18
bootmem_platform_add_ranges(void)19 void bootmem_platform_add_ranges(void)
20 {
21 uintptr_t begin;
22 size_t size;
23 carveout_range(CARVEOUT_TZ, &begin, &size);
24 if (size == 0)
25 return;
26 bootmem_add_range(begin * MiB, size * MiB, BM_MEM_BL31);
27 }
28
soc_read_resources(struct device * dev)29 static void soc_read_resources(struct device *dev)
30 {
31 unsigned long index = 0;
32 int i; uintptr_t begin, end;
33 size_t size;
34
35 for (i = CARVEOUT_TZ + 1; i < CARVEOUT_NUM; i++) {
36 carveout_range(i, &begin, &size);
37 if (size == 0)
38 continue;
39 reserved_ram_range(dev, index++, begin * MiB, size * MiB);
40 }
41
42 memory_in_range_below_4gb(&begin, &end);
43 ram_from_to(dev, index++, begin * MiB, end * MiB);
44
45 memory_in_range_above_4gb(&begin, &end);
46 ram_from_to(dev, index++, begin * MiB, end * MiB);
47 }
48
49 static struct device_operations soc_ops = {
50 .read_resources = soc_read_resources,
51 .set_resources = noop_set_resources,
52 };
53
enable_tegra210_dev(struct device * dev)54 static void enable_tegra210_dev(struct device *dev)
55 {
56 if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
57 dev->ops = &soc_ops;
58
59 if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT))
60 return;
61
62 if (display_init_required())
63 display_startup(dev);
64 else
65 printk(BIOS_INFO, "Skipping display init.\n");
66 }
67
tegra210_init(void * chip_info)68 static void tegra210_init(void *chip_info)
69 {
70 struct tegra_revision rev;
71
72 tegra_revision_info(&rev);
73
74 printk(BIOS_INFO, "chip %x rev %02x.%x\n",
75 rev.chip_id, rev.major, rev.minor);
76
77 /* Save sdram parameters to scratch regs to be used in LP0 resume */
78 sdram_lp0_save_params(get_sdram_config());
79 printk(BIOS_INFO, "sdram params saved.\n");
80 }
81
82 struct chip_operations soc_nvidia_tegra210_ops = {
83 .name = "SOC Nvidia Tegra210",
84 .init = tegra210_init,
85 .enable_dev = enable_tegra210_dev,
86 };
87
enable_plld(void * unused)88 static void enable_plld(void *unused)
89 {
90 /*
91 * Configure a conservative 300MHz clock for PLLD. The kernel cannot
92 * handle PLLD not being configured so enable PLLD unconditionally
93 * with a default clock rate.
94 */
95 clock_configure_plld(300 * MHz);
96 }
97
98 /*
99 * The PLLD being enabled is done at BS_DEV_INIT time because mainboard_init()
100 * is the first thing called. This ensures PLLD is up and functional before
101 * anything that mainboard can do that implicitly relies on PLLD.
102 */
103 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, enable_plld, NULL);
104