1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/mmio.h>
4 #include <delay.h>
5 #include <soc/clock.h>
6 #include <types.h>
7
8 /**
9 * uart_pll_vote_clk_enable - enables PLL8
10 */
uart_pll_vote_clk_enable(unsigned int clk_dummy)11 void uart_pll_vote_clk_enable(unsigned int clk_dummy)
12 {
13 setbits32(BB_PLL_ENA_SC0_REG, BIT(8));
14
15 if (!clk_dummy)
16 while ((read32(PLL_LOCK_DET_STATUS_REG) & BIT(8)) == 0);
17 }
18
19 /**
20 * uart_set_rate_mnd - configures divider M and D values
21 *
22 * Sets the M, D parameters of the divider to generate the GSBI UART
23 * apps clock.
24 */
uart_set_rate_mnd(unsigned int gsbi_port,unsigned int m,unsigned int n)25 static void uart_set_rate_mnd(unsigned int gsbi_port, unsigned int m,
26 unsigned int n)
27 {
28 /* Assert MND reset. */
29 setbits32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7));
30 /* Program M and D values. */
31 write32(GSBIn_UART_APPS_MD_REG(gsbi_port), MD16(m, n));
32 /* Deassert MND reset. */
33 clrbits32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7));
34 }
35
36 /**
37 * uart_branch_clk_enable_reg - enables branch clock
38 *
39 * Enables branch clock for GSBI UART port.
40 */
uart_branch_clk_enable_reg(unsigned int gsbi_port)41 static void uart_branch_clk_enable_reg(unsigned int gsbi_port)
42 {
43 setbits32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(9));
44 }
45
46 /**
47 * uart_local_clock_enable - configures N value and enables root clocks
48 *
49 * Sets the N parameter of the divider and enables root clock and
50 * branch clocks for GSBI UART port.
51 */
uart_local_clock_enable(unsigned int gsbi_port,unsigned int n,unsigned int m)52 static void uart_local_clock_enable(unsigned int gsbi_port, unsigned int n,
53 unsigned int m)
54 {
55 unsigned int reg_val, uart_ns_val;
56 void *const reg = (void *)GSBIn_UART_APPS_NS_REG(gsbi_port);
57
58 /*
59 * Program the NS register, if applicable. NS registers are not
60 * set in the set_rate path because power can be saved by deferring
61 * the selection of a clocked source until the clock is enabled.
62 */
63 reg_val = read32(reg); // REG(0x29D4+(0x20*((n)-1)))
64 reg_val &= ~(Uart_clk_ns_mask);
65 uart_ns_val = NS(BIT_POS_31,BIT_POS_16,n,m, 5, 4, 3, 1, 2, 0,3);
66 reg_val |= (uart_ns_val & Uart_clk_ns_mask);
67 write32(reg, reg_val);
68
69 /* enable MNCNTR_EN */
70 reg_val = read32(reg);
71 reg_val |= BIT(8);
72 write32(reg, reg_val);
73
74 /* set source to PLL8 running @384MHz */
75 reg_val = read32(reg);
76 reg_val |= 0x3;
77 write32(reg, reg_val);
78
79 /* Enable root. */
80 reg_val |= Uart_en_mask;
81 write32(reg, reg_val);
82 uart_branch_clk_enable_reg(gsbi_port);
83 }
84
85 /**
86 * uart_set_gsbi_clk - enables HCLK for UART GSBI port
87 */
uart_set_gsbi_clk(unsigned int gsbi_port)88 static void uart_set_gsbi_clk(unsigned int gsbi_port)
89 {
90 setbits32(GSBIn_HCLK_CTL_REG(gsbi_port), BIT(4));
91 }
92
93 /**
94 * uart_clock_config - configures UART clocks
95 *
96 * Configures GSBI UART dividers, enable root and branch clocks.
97 */
uart_clock_config(unsigned int gsbi_port,unsigned int m,unsigned int n,unsigned int d,unsigned int clk_dummy)98 void uart_clock_config(unsigned int gsbi_port, unsigned int m,
99 unsigned int n, unsigned int d, unsigned int clk_dummy)
100 {
101 uart_set_rate_mnd(gsbi_port, m, d);
102 uart_pll_vote_clk_enable(clk_dummy);
103 uart_local_clock_enable(gsbi_port, n, m);
104 uart_set_gsbi_clk(gsbi_port);
105 }
106
107 /**
108 * nand_clock_config - configure NAND controller clocks
109 *
110 * Enable clocks to EBI2. Must be invoked before touching EBI2
111 * registers.
112 */
nand_clock_config(void)113 void nand_clock_config(void)
114 {
115 write32(EBI2_CLK_CTL_REG,
116 CLK_BRANCH_ENA(1) | ALWAYS_ON_CLK_BRANCH_ENA(1));
117
118 /* Wait for clock to stabilize. */
119 udelay(10);
120 }
121
122 /**
123 * usb_clock_config - configure USB controller clocks and reset the controller
124 */
usb_clock_config(void)125 void usb_clock_config(void)
126 {
127 /* Magic clock initialization numbers, nobody knows how they work... */
128 write32(USB30_MASTER_CLK_CTL_REG, 0x10);
129 write32(USB30_1_MASTER_CLK_CTL_REG, 0x10);
130 write32(USB30_MASTER_CLK_MD, 0x500DF);
131 write32(USB30_MASTER_CLK_NS, 0xE40942);
132 write32(USB30_MOC_UTMI_CLK_MD, 0x100D7);
133 write32(USB30_MOC_UTMI_CLK_NS, 0xD80942);
134 write32(USB30_MOC_UTMI_CLK_CTL, 0x10);
135 write32(USB30_1_MOC_UTMI_CLK_CTL, 0x10);
136
137 write32(USB30_RESET,
138 1 << 5 | /* assert port2 HS PHY async reset */
139 1 << 4 | /* assert master async reset */
140 1 << 3 | /* assert sleep async reset */
141 1 << 2 | /* assert MOC UTMI async reset */
142 1 << 1 | /* assert power-on async reset */
143 1 << 0); /* assert PHY async reset */
144 udelay(5);
145 write32(USB30_RESET, 0); /* deassert all USB resets again */
146 }
147