1 /* SPDX-License-Identifier: BSD-3-Clause */
2
3 #include <device/mmio.h>
4 #include <console/console.h>
5 #include <delay.h>
6 #include <timer.h>
7 #include <soc/gpio.h>
8 #include <soc/iomap.h>
9 #include <soc/qup.h>
10
11 #define TIMEOUT_CNT 100
12
13 #define QUP_ADDR(id, reg) (blsp_qup_base(id) + (reg))
14
15 #define QUP_DEBUG 0
16
17 #define QUPDBG BIOS_ERR, "\t-> "
18
19 #if QUP_DEBUG
20 #define qup_write32(a, v) do { \
21 write32(a, v); \
22 printk(QUPDBG "%s(%d): write32(%p, 0x%x)\n", \
23 __func__, __LINE__, a, v); \
24 } while (0)
25 #else
26 #define qup_write32 write32
27 #endif
28
29 struct i2c_clk_div_fld {
30 u32 clk_freq_out;
31 u8 fs_div;
32 u8 ht_div;
33 };
34
35 static struct i2c_clk_div_fld i2c_clk_div_map[] = {
36 {100000, 124, 62},
37 {400000, 28, 14},
38 {1000000, 8, 5},
39 };
40
i2c_set_mstr_clk_ctl(unsigned int id,unsigned int hz)41 static void i2c_set_mstr_clk_ctl(unsigned int id, unsigned int hz)
42 {
43 int i;
44 struct i2c_clk_div_fld *itr = i2c_clk_div_map;
45 u8 fs_div = 0;
46 u8 ht_div = 0;
47 u32 mstr_clk_ctl;
48
49 for (i = 0; i < ARRAY_SIZE(i2c_clk_div_map); ++i, ++itr) {
50 if (hz == itr->clk_freq_out) {
51 if (!fs_div)
52 fs_div = itr->fs_div;
53 if (!ht_div)
54 ht_div = itr->ht_div;
55 break;
56 }
57 }
58
59 /* format values in clk-ctl cache */
60 mstr_clk_ctl = ((ht_div & 0xff) << 16) | (fs_div & 0xff);
61 qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_CLK_CTL), mstr_clk_ctl);
62 }
63
qup_i2c_master_status(blsp_qup_id_t id)64 static qup_return_t qup_i2c_master_status(blsp_qup_id_t id)
65 {
66 uint32_t reg_val = read32(QUP_ADDR(id, QUP_I2C_MASTER_STATUS));
67
68 if (read32(QUP_ADDR(id, QUP_ERROR_FLAGS)))
69 return QUP_ERR_XFER_FAIL;
70
71 #if QUP_DEBUG
72 printk(QUPDBG "%s: 0x%x\n", __func__, reg_val);
73 #endif
74
75 if (reg_val & QUP_I2C_INVALID_READ_ADDR)
76 return QUP_ERR_I2C_INVALID_SLAVE_ADDR;
77 if (reg_val & QUP_I2C_FAILED_MASK)
78 return QUP_ERR_I2C_FAILED;
79 if (reg_val & QUP_I2C_ARB_LOST)
80 return QUP_ERR_I2C_ARB_LOST;
81 if (reg_val & QUP_I2C_BUS_ERROR)
82 return QUP_ERR_I2C_BUS_ERROR;
83 if (reg_val & QUP_I2C_INVALID_WRITE)
84 return QUP_ERR_I2C_INVALID_WRITE;
85 if (reg_val & QUP_I2C_PACKET_NACK)
86 return QUP_ERR_I2C_NACK;
87 if (reg_val & QUP_I2C_INVALID_TAG)
88 return QUP_ERR_I2C_INVALID_TAG;
89
90 return QUP_SUCCESS;
91 }
92
check_bit_state(uint32_t * reg,int wait_for)93 static int check_bit_state(uint32_t *reg, int wait_for)
94 {
95 unsigned int count = TIMEOUT_CNT;
96
97 while ((read32(reg) & (QUP_STATE_VALID_MASK | QUP_STATE_MASK)) !=
98 (QUP_STATE_VALID | wait_for)) {
99 if (count == 0)
100 return QUP_ERR_TIMEOUT;
101 count--;
102 }
103
104 return QUP_SUCCESS;
105 }
106
107 /*
108 * Check whether GSBIn_QUP State is valid
109 */
qup_wait_for_state(blsp_qup_id_t id,unsigned int wait_for)110 static qup_return_t qup_wait_for_state(blsp_qup_id_t id, unsigned int wait_for)
111 {
112 return check_bit_state(QUP_ADDR(id, QUP_STATE), wait_for);
113 }
114
qup_reset_i2c_master_status(blsp_qup_id_t id)115 qup_return_t qup_reset_i2c_master_status(blsp_qup_id_t id)
116 {
117 /*
118 * The I2C_STATUS is a status register.
119 * Writing any value clears the status bits.
120 */
121 qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_STATUS), 0);
122 return QUP_SUCCESS;
123 }
124
qup_reset_master_status(blsp_qup_id_t id)125 static qup_return_t qup_reset_master_status(blsp_qup_id_t id)
126 {
127 qup_write32(QUP_ADDR(id, QUP_ERROR_FLAGS), 0x3C);
128 qup_write32(QUP_ADDR(id, QUP_ERROR_FLAGS_EN), 0x3C);
129 qup_reset_i2c_master_status(id);
130 return QUP_SUCCESS;
131 }
132
qup_fifo_wait_for(blsp_qup_id_t id,uint32_t status,struct stopwatch * timeout)133 static qup_return_t qup_fifo_wait_for(blsp_qup_id_t id, uint32_t status,
134 struct stopwatch *timeout)
135 {
136 qup_return_t ret = QUP_ERR_UNDEFINED;
137
138 while (!(read32(QUP_ADDR(id, QUP_OPERATIONAL)) & status)) {
139 ret = qup_i2c_master_status(id);
140 if (ret)
141 return ret;
142 if (stopwatch_expired(timeout))
143 return QUP_ERR_TIMEOUT;
144 }
145
146 return QUP_SUCCESS;
147 }
148
qup_fifo_wait_while(blsp_qup_id_t id,uint32_t status,struct stopwatch * timeout)149 static qup_return_t qup_fifo_wait_while(blsp_qup_id_t id, uint32_t status,
150 struct stopwatch *timeout)
151 {
152 qup_return_t ret = QUP_ERR_UNDEFINED;
153
154 while (read32(QUP_ADDR(id, QUP_OPERATIONAL)) & status) {
155 ret = qup_i2c_master_status(id);
156 if (ret)
157 return ret;
158 if (stopwatch_expired(timeout))
159 return QUP_ERR_TIMEOUT;
160 }
161
162 return QUP_SUCCESS;
163 }
164
qup_i2c_create_output_tag(int stop,u8 data)165 static inline uint32_t qup_i2c_create_output_tag(int stop, u8 data)
166 {
167 uint32_t tag;
168
169 if (stop)
170 tag = QUP_I2C_STOP_SEQ | QUP_I2C_DATA(data);
171 else
172 tag = QUP_I2C_DATA_SEQ | QUP_I2C_DATA(data);
173
174 return tag;
175 }
176
qup_i2c_write_fifo_flush(blsp_qup_id_t id,struct stopwatch * timeout)177 static inline qup_return_t qup_i2c_write_fifo_flush(blsp_qup_id_t id,
178 struct stopwatch *timeout)
179 {
180 qup_return_t ret = QUP_ERR_UNDEFINED;
181
182 qup_write32(QUP_ADDR(id, QUP_OPERATIONAL), OUTPUT_SERVICE_FLAG);
183
184 mdelay(4); /* TPM seems to need this */
185
186 ret = qup_fifo_wait_while(id, OUTPUT_FIFO_NOT_EMPTY, timeout);
187 if (ret)
188 return ret;
189
190 ret = qup_i2c_master_status(id);
191
192 if (ret)
193 printk(BIOS_DEBUG, "%s: error\n", __func__);
194
195 return ret;
196 }
197
qup_i2c_write_fifo(blsp_qup_id_t id,qup_data_t * p_tx_obj,uint8_t stop_seq)198 static qup_return_t qup_i2c_write_fifo(blsp_qup_id_t id, qup_data_t *p_tx_obj,
199 uint8_t stop_seq)
200 {
201 qup_return_t ret = QUP_ERR_UNDEFINED;
202 uint8_t addr = p_tx_obj->p.iic.addr;
203 uint8_t *data_ptr = p_tx_obj->p.iic.data;
204 unsigned int data_len = p_tx_obj->p.iic.data_len;
205 unsigned int idx = 0;
206 uint32_t tag, *fifo = QUP_ADDR(id, QUP_OUTPUT_FIFO);
207 struct stopwatch timeout;
208
209 qup_reset_master_status(id);
210
211 qup_write32(QUP_ADDR(id, QUP_MX_OUTPUT_COUNT), data_len + 1);
212
213 qup_set_state(id, QUP_STATE_RUN);
214
215 /*
216 * Since UNPACK enable is set in io mode register, populate 2 tags
217 * for each fifo register.
218 *
219 * Create the first tag as follows, with the start tag and first byte
220 * of the data to be written
221 * +--------+--------+--------+--------+
222 * | STOP / | data | START | ADDR |
223 * |DATA tag| byte | tag | << 1 |
224 * +--------+--------+--------+--------+
225 * rest will be created in the following while loop.
226 */
227 tag = qup_i2c_create_output_tag(data_len == 1 && stop_seq,
228 data_ptr[idx]);
229 tag = ((tag << 16) & 0xffff0000) |
230 (QUP_I2C_START_SEQ | QUP_I2C_ADDR(addr));
231 data_len--;
232 idx++;
233
234 qup_write32(fifo, tag);
235
236 stopwatch_init_usecs_expire(&timeout, CONFIG_I2C_TRANSFER_TIMEOUT_US);
237 while (data_len) {
238 tag = qup_i2c_create_output_tag(data_len == 1 && stop_seq,
239 data_ptr[idx]);
240 data_len--;
241 idx++;
242
243 if (data_len) {
244 tag |= qup_i2c_create_output_tag(
245 data_len == 1 && stop_seq,
246 data_ptr[idx]) << 16;
247 data_len--;
248 idx++;
249 }
250
251 qup_write32(fifo, tag);
252
253 ret = qup_i2c_write_fifo_flush(id, &timeout);
254
255 if (ret) {
256 printk(QUPDBG "%s: error\n", __func__);
257 return ret;
258 }
259 }
260
261 ret = qup_i2c_write_fifo_flush(id, &timeout);
262
263 qup_set_state(id, QUP_STATE_RESET);
264
265 return ret;
266 }
267
qup_i2c_write(blsp_qup_id_t id,uint8_t mode,qup_data_t * p_tx_obj,uint8_t stop_seq)268 static qup_return_t qup_i2c_write(blsp_qup_id_t id, uint8_t mode,
269 qup_data_t *p_tx_obj, uint8_t stop_seq)
270 {
271 qup_return_t ret = QUP_ERR_UNDEFINED;
272
273 switch (mode) {
274 case QUP_MODE_FIFO:
275 case QUP_MODE_BLOCK:
276 ret = qup_i2c_write_fifo(id, p_tx_obj, stop_seq);
277 break;
278 default:
279 ret = QUP_ERR_UNSUPPORTED;
280 }
281
282 if (ret) {
283 qup_set_state(id, QUP_STATE_RESET);
284 printk(QUPDBG "%s() failed (%d)\n", __func__, ret);
285 }
286
287 return ret;
288 }
289
qup_i2c_parse_tag(uint32_t data,uint8_t * data_ptr,uint32_t len)290 static int qup_i2c_parse_tag(uint32_t data, uint8_t *data_ptr, uint32_t len)
291 {
292 int i, idx = 0;
293 int max = (len > 2) ? 2 : len;
294
295 for (i = 0; i < max; i++) {
296 switch (QUP_I2C_MI_TAG(data)) {
297 case QUP_I2C_MIDATA_SEQ:
298 data_ptr[idx] = QUP_I2C_DATA(data);
299 idx++;
300 break;
301 case QUP_I2C_MISTOP_SEQ:
302 data_ptr[idx] = QUP_I2C_DATA(data);
303 idx++;
304 return idx;
305 default:
306 printk(QUPDBG "%s: Unexpected tag (0x%x)\n", __func__,
307 QUP_I2C_MI_TAG(data));
308 return -1;
309 }
310
311 data = (data >> 16);
312 }
313
314 return idx;
315 }
316
qup_i2c_read_fifo(blsp_qup_id_t id,qup_data_t * p_tx_obj)317 static qup_return_t qup_i2c_read_fifo(blsp_qup_id_t id, qup_data_t *p_tx_obj)
318 {
319 qup_return_t ret = QUP_ERR_UNDEFINED;
320 uint8_t addr = p_tx_obj->p.iic.addr;
321 uint8_t *data_ptr = p_tx_obj->p.iic.data;
322 unsigned int data_len = p_tx_obj->p.iic.data_len;
323 unsigned int idx = 0;
324 uint32_t *fifo = QUP_ADDR(id, QUP_OUTPUT_FIFO);
325 struct stopwatch timeout;
326
327 qup_reset_master_status(id);
328
329 qup_write32(QUP_ADDR(id, QUP_IO_MODES),
330 QUP_UNPACK_EN | QUP_PACK_EN |
331 ((QUP_MODE_BLOCK & QUP_MODE_MASK) <<
332 QUP_OUTPUT_MODE_SHFT) |
333 ((QUP_MODE_BLOCK & QUP_MODE_MASK) <<
334 QUP_INPUT_MODE_SHFT));
335
336 qup_write32(QUP_ADDR(id, QUP_MX_INPUT_COUNT), data_len);
337
338 qup_set_state(id, QUP_STATE_RUN);
339
340 qup_write32(fifo, (QUP_I2C_START_SEQ |
341 (QUP_I2C_ADDR(addr) | QUP_I2C_SLAVE_READ)) |
342 ((QUP_I2C_RECV_SEQ | data_len) << 16));
343
344 stopwatch_init_usecs_expire(&timeout, CONFIG_I2C_TRANSFER_TIMEOUT_US);
345 ret = qup_i2c_write_fifo_flush(id, &timeout);
346 if (ret) {
347 printk(QUPDBG "%s: OUTPUT_FIFO_NOT_EMPTY\n", __func__);
348 return ret;
349 }
350
351 ret = qup_fifo_wait_for(id, INPUT_SERVICE_FLAG, &timeout);
352 if (ret) {
353 printk(QUPDBG "%s: INPUT_SERVICE_FLAG\n", __func__);
354 return ret;
355 }
356
357 fifo = QUP_ADDR(id, QUP_INPUT_FIFO);
358
359 while (data_len) {
360 uint32_t data;
361 int count;
362
363 data = read32(fifo);
364 mdelay(1);
365
366 count = qup_i2c_parse_tag(data, data_ptr + idx, data_len);
367
368 if (count < 0) {
369 printk(QUPDBG "%s: Cannot parse tag 0x%x\n",
370 __func__, data);
371 qup_set_state(id, QUP_STATE_PAUSE);
372
373 return QUP_ERR_I2C_INVALID_TAG;
374 }
375
376 idx += count;
377 data_len -= count;
378
379 qup_write32(QUP_ADDR(id, QUP_OPERATIONAL), INPUT_SERVICE_FLAG);
380 }
381
382 p_tx_obj->p.iic.data_len = idx;
383
384 qup_write32(QUP_ADDR(id, QUP_MX_READ_COUNT), 0);
385
386 qup_set_state(id, QUP_STATE_RESET);
387
388 return QUP_SUCCESS;
389 }
390
qup_i2c_read(blsp_qup_id_t id,uint8_t mode,qup_data_t * p_tx_obj)391 static qup_return_t qup_i2c_read(blsp_qup_id_t id, uint8_t mode,
392 qup_data_t *p_tx_obj)
393 {
394 qup_return_t ret = QUP_ERR_UNDEFINED;
395
396 qup_set_state(id, QUP_STATE_RESET);
397
398 switch (mode) {
399 case QUP_MODE_FIFO:
400 case QUP_MODE_BLOCK:
401 ret = qup_i2c_read_fifo(id, p_tx_obj);
402 break;
403 default:
404 ret = QUP_ERR_UNSUPPORTED;
405 }
406
407 if (ret) {
408 qup_set_state(id, QUP_STATE_RESET);
409 printk(QUPDBG "%s() failed (%d)\n", __func__, ret);
410 }
411
412 return ret;
413 }
414
qup_init(blsp_qup_id_t id,const qup_config_t * config_ptr)415 qup_return_t qup_init(blsp_qup_id_t id, const qup_config_t *config_ptr)
416 {
417 qup_return_t ret = QUP_ERR_UNDEFINED;
418 uint32_t reg_val;
419
420 /* Reset the QUP core.*/
421 qup_write32(QUP_ADDR(id, QUP_SW_RESET), 0x1);
422
423 /* Wait till the reset takes effect */
424 ret = qup_wait_for_state(id, QUP_STATE_RESET);
425 if (ret)
426 goto bailout;
427
428 /* Reset the config */
429 qup_write32(QUP_ADDR(id, QUP_CONFIG), 0);
430
431 /* Program the config register */
432 /* Set N value */
433 reg_val = 0x0F;
434 /* Set protocol */
435 switch (config_ptr->protocol) {
436 case QUP_MINICORE_I2C_MASTER:
437 reg_val |= ((config_ptr->protocol &
438 QUP_MINI_CORE_PROTO_MASK) <<
439 QUP_MINI_CORE_PROTO_SHFT);
440 break;
441 default:
442 ret = QUP_ERR_UNSUPPORTED;
443 goto bailout;
444 }
445 reg_val |= QUP_APP_CLK_ON_EN | QUP_CORE_CLK_ON_EN;
446 qup_write32(QUP_ADDR(id, QUP_CONFIG), reg_val);
447
448 /* Choose version 1 tag */
449 qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_CONFIG), 0);
450
451 /* Reset i2c clk cntl register */
452 qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_CLK_CTL), 0);
453
454 /* Set QUP IO Mode */
455 switch (config_ptr->mode) {
456 case QUP_MODE_FIFO:
457 case QUP_MODE_BLOCK:
458 reg_val = QUP_UNPACK_EN | QUP_PACK_EN |
459 ((config_ptr->mode & QUP_MODE_MASK) <<
460 QUP_OUTPUT_MODE_SHFT) |
461 ((config_ptr->mode & QUP_MODE_MASK) <<
462 QUP_INPUT_MODE_SHFT);
463 break;
464 default:
465 ret = QUP_ERR_UNSUPPORTED;
466 goto bailout;
467 }
468 qup_write32(QUP_ADDR(id, QUP_IO_MODES), reg_val);
469
470 /*Set i2c clk cntl*/
471 i2c_set_mstr_clk_ctl(id, 400000);
472
473 qup_set_state(id, QUP_STATE_RESET);
474 bailout:
475 if (ret)
476 printk(QUPDBG "failed to init qup (%d)\n", ret);
477
478 return ret;
479 }
480
qup_set_state(blsp_qup_id_t id,uint32_t state)481 qup_return_t qup_set_state(blsp_qup_id_t id, uint32_t state)
482 {
483 qup_return_t ret = QUP_ERR_UNDEFINED;
484 unsigned int curr_state = read32(QUP_ADDR(id, QUP_STATE));
485
486 if ((state <= QUP_STATE_PAUSE)
487 && (curr_state & QUP_STATE_VALID_MASK)) {
488 /*
489 * For PAUSE_STATE to RESET_STATE transition,
490 * two writes of 10[binary]) are required for the
491 * transition to complete.
492 */
493 if (curr_state == QUP_STATE_PAUSE && state == QUP_STATE_RESET) {
494 qup_write32(QUP_ADDR(id, QUP_STATE), 0x2);
495 qup_write32(QUP_ADDR(id, QUP_STATE), 0x2);
496 } else {
497 qup_write32(QUP_ADDR(id, QUP_STATE), state);
498 }
499 ret = qup_wait_for_state(id, state);
500 }
501
502 return ret;
503 }
504
qup_i2c_send_data(blsp_qup_id_t id,qup_data_t * p_tx_obj,uint8_t stop_seq)505 static qup_return_t qup_i2c_send_data(blsp_qup_id_t id, qup_data_t *p_tx_obj,
506 uint8_t stop_seq)
507 {
508 qup_return_t ret = QUP_ERR_UNDEFINED;
509 uint8_t mode = (read32(QUP_ADDR(id, QUP_IO_MODES)) >>
510 QUP_OUTPUT_MODE_SHFT) & QUP_MODE_MASK;
511
512 ret = qup_i2c_write(id, mode, p_tx_obj, stop_seq);
513 if (QUP_DEBUG) {
514 int i;
515
516 printk(BIOS_DEBUG, "i2c tx bus %d device %2.2x:",
517 id, p_tx_obj->p.iic.addr);
518 for (i = 0; i < p_tx_obj->p.iic.data_len; i++)
519 printk(BIOS_DEBUG, " %2.2x", p_tx_obj->p.iic.data[i]);
520 printk(BIOS_DEBUG, "\n");
521 }
522
523 return ret;
524 }
525
qup_send_data(blsp_qup_id_t id,qup_data_t * p_tx_obj,uint8_t stop_seq)526 qup_return_t qup_send_data(blsp_qup_id_t id, qup_data_t *p_tx_obj,
527 uint8_t stop_seq)
528 {
529 qup_return_t ret = QUP_ERR_UNDEFINED;
530
531 if (p_tx_obj->protocol == ((read32(QUP_ADDR(id, QUP_CONFIG)) >>
532 QUP_MINI_CORE_PROTO_SHFT) & QUP_MINI_CORE_PROTO_MASK)) {
533 switch (p_tx_obj->protocol) {
534 case QUP_MINICORE_I2C_MASTER:
535 ret = qup_i2c_send_data(id, p_tx_obj, stop_seq);
536 break;
537 default:
538 ret = QUP_ERR_UNSUPPORTED;
539 }
540 }
541
542 return ret;
543 }
544
qup_i2c_recv_data(blsp_qup_id_t id,qup_data_t * p_rx_obj)545 static qup_return_t qup_i2c_recv_data(blsp_qup_id_t id, qup_data_t *p_rx_obj)
546 {
547 qup_return_t ret = QUP_ERR_UNDEFINED;
548 uint8_t mode = (read32(QUP_ADDR(id, QUP_IO_MODES)) >>
549 QUP_INPUT_MODE_SHFT) & QUP_MODE_MASK;
550
551 ret = qup_i2c_read(id, mode, p_rx_obj);
552 if (QUP_DEBUG) {
553 int i;
554
555 printk(BIOS_DEBUG, "i2c rxed on bus %d device %2.2x:",
556 id, p_rx_obj->p.iic.addr);
557 for (i = 0; i < p_rx_obj->p.iic.data_len; i++)
558 printk(BIOS_DEBUG, " %2.2x", p_rx_obj->p.iic.data[i]);
559 printk(BIOS_DEBUG, "\n");
560 }
561
562 return ret;
563 }
564
qup_recv_data(blsp_qup_id_t id,qup_data_t * p_rx_obj)565 qup_return_t qup_recv_data(blsp_qup_id_t id, qup_data_t *p_rx_obj)
566 {
567 qup_return_t ret = QUP_ERR_UNDEFINED;
568
569 if (p_rx_obj->protocol == ((read32(QUP_ADDR(id, QUP_CONFIG)) >>
570 QUP_MINI_CORE_PROTO_SHFT) & QUP_MINI_CORE_PROTO_MASK)) {
571 switch (p_rx_obj->protocol) {
572 case QUP_MINICORE_I2C_MASTER:
573 ret = qup_i2c_recv_data(id, p_rx_obj);
574 break;
575 default:
576 ret = QUP_ERR_UNSUPPORTED;
577 }
578 }
579
580 return ret;
581 }
582