1/* SPDX-License-Identifier: GPL-2.0-only */ 2 3#include <memlayout.h> 4#include <arch/header.ld> 5 6SECTIONS 7{ 8 DRAM_START(0x00000000) 9 BL31(0, 0x100000) 10 POSTRAM_CBFS_CACHE(0x00100000, 8M) 11 RAMSTAGE(0x00900000, 2M) 12 DMA_COHERENT(0x10000000, 2M) 13 14 /* 8K of special SRAM in PMU power domain. */ 15 REGION_START(pmu_sram, 0xFF3B0000) 16 WATCHDOG_TOMBSTONE(0xFF3B1FFC, 4) 17 REGION_END(pmu_sram, 0xFF3B2000) 18 19 SRAM_START(0xFF8C0000) 20#if ENV_RAMSTAGE 21 REGION(bl31_sram, 0xFF8C0000, 64K, 1) 22#else 23 PRERAM_CBFS_CACHE(0xFF8C0000, 5K) 24 FMAP_CACHE(0xFF8C1400, 2K) 25 TIMESTAMP(0xFF8C1C00, 1K) 26 /* 0xFF8C2004 is the entry point address the masked ROM will jump to. */ 27 OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 84K - 4) 28 BOOTBLOCK(0xFF8D7000, 40K) 29#endif 30 CBFS_MCACHE(0xFF8E1000, 8K) 31 VBOOT2_WORK(0XFF8E3000, 12K) 32 TTB(0xFF8E6000, 20K) 33 PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K) 34 STACK(0xFF8ED000, 12K) 35 SRAM_END(0xFF8F0000) 36} 37