1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <arch/cache.h>
4 #include <bootblock_common.h>
5 #include <soc/clk.h>
6 #include <soc/wakeup.h>
7 #include <soc/cpu.h>
8
9 /* convenient shorthand (in MB) */
10 #define SRAM_START (EXYNOS5_SRAM_BASE >> 20)
11 #define SRAM_SIZE 1
12 #define SRAM_END (SRAM_START + SRAM_SIZE) /* plus one... */
13
bootblock_soc_init(void)14 void bootblock_soc_init(void)
15 {
16 if (get_wakeup_state() == WAKEUP_DIRECT) {
17 wakeup();
18 /* Never returns. */
19 }
20
21 /* set up dcache and MMU */
22 mmu_init();
23 mmu_disable_range(0, SRAM_START);
24 mmu_config_range(SRAM_START, SRAM_SIZE, DCACHE_WRITEBACK);
25 mmu_config_range(SRAM_END, 4096 - SRAM_END, DCACHE_OFF);
26 dcache_mmu_enable();
27
28 /* For most ARM systems, we have to initialize firmware media source
29 * (ex, SPI, SD/MMC, or eMMC) now; but for Exynos platform, that is
30 * already handled by iROM so there's no need to setup again.
31 */
32 }
33