1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <soc/sdram.h> 4 #include <soc/addressmap.h> 5 6 #include "regconfig-phy.h" 7 #include "regconfig-ctl.h" 8 #include "ux00ddr.h" 9 10 #define DENALI_PHY_DATA ddr_phy_settings 11 #define DENALI_CTL_DATA ddr_ctl_settings 12 #include "ddrregs.h" 13 14 #define DDR_SIZE (8UL * 1024UL * 1024UL * 1024UL) 15 sdram_init(void)16void sdram_init(void) 17 { 18 ux00ddr_writeregmap(FU540_DDRCTRL, ddr_ctl_settings, ddr_phy_settings); 19 ux00ddr_disableaxireadinterleave(FU540_DDRCTRL); 20 21 ux00ddr_disableoptimalrmodw(FU540_DDRCTRL); 22 23 ux00ddr_enablewriteleveling(FU540_DDRCTRL); 24 ux00ddr_enablereadleveling(FU540_DDRCTRL); 25 ux00ddr_enablereadlevelinggate(FU540_DDRCTRL); 26 if (ux00ddr_getdramclass(FU540_DDRCTRL) == DRAM_CLASS_DDR4) 27 ux00ddr_enablevreftraining(FU540_DDRCTRL); 28 29 //mask off interrupts for leveling completion 30 ux00ddr_mask_leveling_completed_interrupt(FU540_DDRCTRL); 31 32 ux00ddr_mask_mc_init_complete_interrupt(FU540_DDRCTRL); 33 ux00ddr_mask_outofrange_interrupts(FU540_DDRCTRL); 34 ux00ddr_setuprangeprotection(FU540_DDRCTRL, DDR_SIZE); 35 ux00ddr_mask_port_command_error_interrupt(FU540_DDRCTRL); 36 37 const uint64_t ddr_size = DDR_SIZE; 38 const uint64_t ddr_end = FU540_DRAM + ddr_size; 39 ux00ddr_start(FU540_DDRCTRL, FU540_DDRBUSBLOCKER, ddr_end); 40 41 ux00ddr_phy_fixup(FU540_DDRCTRL); 42 } 43 sdram_size_mb(void)44size_t sdram_size_mb(void) 45 { 46 static size_t size_mb = 0; 47 48 if (!size_mb) { 49 // TODO: implement 50 size_mb = 8 * 1024; 51 } 52 53 return size_mb; 54 } 55