1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <amdblocks/acpimmio.h>
4 #include <console/console.h>
5 #include <device/device.h>
6 #include <device/pci.h>
7 #include <device/pnp.h>
8 #include <device/pci_ids.h>
9 #include <device/pci_ops.h>
10 #include <pc80/mc146818rtc.h>
11 #include <pc80/isa-dma.h>
12 #include <arch/io.h>
13 #include <arch/ioapic.h>
14 #include <acpi/acpi.h>
15 #include <pc80/i8254.h>
16 #include <pc80/i8259.h>
17 #include <types.h>
18
19 #include "hudson.h"
20 #include "pci_devs.h"
21
lpc_init(struct device * dev)22 static void lpc_init(struct device *dev)
23 {
24 u8 byte;
25 u32 dword;
26 struct device *sm_dev;
27
28 /* Enable the LPC Controller */
29 sm_dev = pcidev_on_root(0x14, 0);
30 dword = pci_read_config32(sm_dev, 0x64);
31 dword |= 1 << 20;
32 pci_write_config32(sm_dev, 0x64, dword);
33
34 /* Initialize isa dma */
35 isa_dma_init();
36
37 /* Enable DMA transaction on the LPC bus */
38 byte = pci_read_config8(dev, 0x40);
39 byte |= (1 << 2);
40 pci_write_config8(dev, 0x40, byte);
41
42 /* Disable the timeout mechanism on LPC */
43 byte = pci_read_config8(dev, 0x48);
44 byte &= ~(1 << 7);
45 pci_write_config8(dev, 0x48, byte);
46
47 /* Disable LPC MSI Capability */
48 byte = pci_read_config8(dev, 0x78);
49 byte &= ~(1 << 1);
50 byte &= ~(1 << 0); /* Keep the old way. i.e., when bus master/DMA cycle is running
51 on LPC, it holds PCI grant, so no LPC slave cycle can
52 interrupt and visit LPC. */
53 pci_write_config8(dev, 0x78, byte);
54
55 /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */
56 /* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */
57 byte = pci_read_config8(dev, 0xBB);
58 byte |= 1 << 0 | 1 << 3;
59 pci_write_config8(dev, 0xBB, byte);
60
61 cmos_check_update_date();
62
63 /* Initialize the real time clock.
64 * The 0 argument tells cmos_init not to
65 * update CMOS unless it is invalid.
66 * 1 tells cmos_init to always initialize the CMOS.
67 */
68 cmos_init(0);
69
70 /* Initialize i8259 pic */
71 setup_i8259();
72
73 /* Initialize i8254 timers */
74 setup_i8254();
75
76 /* Set up SERIRQ, enable continuous mode */
77 byte = (BIT(4) | BIT(7));
78 if (!CONFIG(SERIRQ_CONTINUOUS_MODE))
79 byte |= BIT(6);
80
81 pm_write8(PM_SERIRQ_CONF, byte);
82 }
83
hudson_lpc_read_resources(struct device * dev)84 static void hudson_lpc_read_resources(struct device *dev)
85 {
86 struct resource *res;
87
88 /* Get the normal pci resources of this device */
89 pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
90
91 /* Add an extra subtractive resource for both memory and I/O. */
92 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
93 res->base = 0;
94 res->size = 0x1000;
95 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
96 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
97
98 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
99 res->base = 0xff800000;
100 res->size = 0x00800000; /* 8 MB for flash */
101 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
102 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
103
104 /* Add a memory resource for the SPI BAR. */
105 mmio_range(dev, 2, SPI_BASE_ADDRESS, 1 * KiB);
106
107 res = new_resource(dev, 3); /* IOAPIC */
108 res->base = IO_APIC_ADDR;
109 res->size = 0x00001000;
110 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
111
112 compact_resources(dev);
113 }
114
hudson_lpc_set_resources(struct device * dev)115 static void hudson_lpc_set_resources(struct device *dev)
116 {
117 struct resource *res;
118 u32 spi_enable_bits;
119
120 /* Special case. The SpiRomEnable and other enables should STAY set. */
121 res = find_resource(dev, 2);
122 spi_enable_bits = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);
123 spi_enable_bits &= 0xF;
124 pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | spi_enable_bits);
125
126 pci_dev_set_resources(dev);
127 }
128
129 /**
130 * @brief Enable resources for children devices
131 *
132 * @param dev the device whose children's resources are to be enabled
133 *
134 */
hudson_lpc_enable_childrens_resources(struct device * dev)135 static void hudson_lpc_enable_childrens_resources(struct device *dev)
136 {
137 u32 reg, reg_x;
138 int var_num = 0;
139 u16 reg_var[3];
140 u16 reg_size[1] = {512};
141 u8 wiosize = pci_read_config8(dev, 0x74);
142
143 /* Be bit relaxed, tolerate that LPC region might be bigger than resource we try to fit,
144 * do it like this for all regions < 16 bytes. If there is a resource > 16 bytes
145 * it must be 512 bytes to be able to allocate the fresh LPC window.
146 *
147 * AGESA likes to enable already one LPC region in wide port base 0x64-0x65,
148 * using DFLT_SIO_PME_BASE_ADDRESS, 512 bytes size
149 * The code tries to check if resource can fit into this region
150 */
151
152 reg = pci_read_config32(dev, 0x44);
153 reg_x = pci_read_config32(dev, 0x48);
154
155 /* check if ranges are free and not use them if entry is just already taken */
156 if (reg_x & (1 << 2))
157 var_num = 1;
158 /* just in case check if someone did not manually set other ranges too */
159 if (reg_x & (1 << 24))
160 var_num = 2;
161
162 if (reg_x & (1 << 25))
163 var_num = 3;
164
165 /* check AGESA region size */
166 if (wiosize & (1 << 0))
167 reg_size[0] = 16;
168
169 reg_var[2] = pci_read_config16(dev, 0x90);
170 reg_var[1] = pci_read_config16(dev, 0x66);
171 reg_var[0] = pci_read_config16(dev, 0x64);
172
173 struct device *child;
174 if (dev->downstream) {
175 for (child = dev->downstream->children; child; child = child->sibling) {
176 if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
177 struct resource *res;
178 for (res = child->resource_list; res; res = res->next) {
179 u32 base, end; /* don't need long long */
180 u32 rsize, set = 0, set_x = 0;
181 if (!(res->flags & IORESOURCE_IO))
182 continue;
183 base = res->base;
184 end = resource_end(res);
185 /* find a resource size */
186 printk(BIOS_DEBUG, "hudson lpc decode:%s, base=0x%08x, end=0x%08x\n",
187 dev_path(child), base, end);
188 switch (base) {
189 case 0x60: /* KB */
190 case 0x64: /* MS */
191 set |= (1 << 29);
192 rsize = 1;
193 break;
194 case 0x3f8: /* COM1 */
195 set |= (1 << 6);
196 rsize = 8;
197 break;
198 case 0x2f8: /* COM2 */
199 set |= (1 << 7);
200 rsize = 8;
201 break;
202 case 0x378: /* Parallel 1 */
203 set |= (1 << 0);
204 set |= (1 << 1); /* + 0x778 for ECP */
205 rsize = 8;
206 break;
207 case 0x3f0: /* FD0 */
208 set |= (1 << 26);
209 rsize = 8;
210 break;
211 case 0x220: /* 0x220 - 0x227 */
212 set |= (1 << 8);
213 rsize = 8;
214 break;
215 case 0x228: /* 0x228 - 0x22f */
216 set |= (1 << 9);
217 rsize = 8;
218 break;
219 case 0x238: /* 0x238 - 0x23f */
220 set |= (1 << 10);
221 rsize = 8;
222 break;
223 case 0x300: /* 0x300 -0x301 */
224 set |= (1 << 18);
225 rsize = 2;
226 break;
227 case 0x400:
228 set_x |= (1 << 16);
229 rsize = 0x40;
230 break;
231 case 0x480:
232 set_x |= (1 << 17);
233 rsize = 0x40;
234 break;
235 case 0x500:
236 set_x |= (1 << 18);
237 rsize = 0x40;
238 break;
239 case 0x580:
240 set_x |= (1 << 19);
241 rsize = 0x40;
242 break;
243 case 0x4700:
244 set_x |= (1 << 22);
245 rsize = 0xc;
246 break;
247 case 0xfd60:
248 set_x |= (1 << 23);
249 rsize = 16;
250 break;
251 default:
252 rsize = 0;
253 /* try AGESA allocated region in region 0 */
254 if ((var_num > 0) && ((base >= reg_var[0]) &&
255 ((base + res->size) <= (reg_var[0] + reg_size[0]))))
256 rsize = reg_size[0];
257 }
258 /* check if region found and matches the enable */
259 if (res->size <= rsize) {
260 reg |= set;
261 reg_x |= set_x;
262 /* check if we can fit resource in variable range */
263 } else if ((var_num < 3) &&
264 ((res->size <= 16) || (res->size == 512))) {
265 /* use variable ranges if pre-defined do not match */
266 switch (var_num) {
267 case 0:
268 reg_x |= (1 << 2);
269 if (res->size <= 16) {
270 wiosize |= (1 << 0);
271 }
272 break;
273 case 1:
274 reg_x |= (1 << 24);
275 if (res->size <= 16)
276 wiosize |= (1 << 2);
277 break;
278 case 2:
279 reg_x |= (1 << 25);
280 if (res->size <= 16)
281 wiosize |= (1 << 3);
282 break;
283 }
284 reg_var[var_num++] =
285 base & 0xffff;
286 } else {
287 printk(BIOS_ERR, "cannot fit LPC decode region:%s, base=0x%08x, end=0x%08x\n",
288 dev_path(child), base, end);
289 }
290 }
291 }
292 }
293 }
294 pci_write_config32(dev, 0x44, reg);
295 pci_write_config32(dev, 0x48, reg_x);
296 /* Set WideIO for as many IOs found (fall through is on purpose) */
297 switch (var_num) {
298 case 3:
299 pci_write_config16(dev, 0x90, reg_var[2]);
300 __fallthrough;
301 case 2:
302 pci_write_config16(dev, 0x66, reg_var[1]);
303 __fallthrough;
304 case 1:
305 pci_write_config16(dev, 0x64, reg_var[0]);
306 break;
307 }
308 pci_write_config8(dev, 0x74, wiosize);
309 }
310
hudson_lpc_enable_resources(struct device * dev)311 static void hudson_lpc_enable_resources(struct device *dev)
312 {
313 pci_dev_enable_resources(dev);
314 hudson_lpc_enable_childrens_resources(dev);
315 }
316
lpc_acpi_name(const struct device * dev)317 static const char *lpc_acpi_name(const struct device *dev)
318 {
319 if (dev->path.type != DEVICE_PATH_PCI)
320 return NULL;
321
322 if (dev->path.pci.devfn == LPC_DEVFN)
323 return "LIBR";
324
325 return NULL;
326 }
327
lpc_final(struct device * dev)328 static void lpc_final(struct device *dev)
329 {
330 if (!acpi_is_wakeup_s3()) {
331 if (CONFIG(HAVE_SMI_HANDLER))
332 outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */
333 else
334 outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
335 }
336 }
337
338 static struct device_operations lpc_ops = {
339 .read_resources = hudson_lpc_read_resources,
340 .set_resources = hudson_lpc_set_resources,
341 .enable_resources = hudson_lpc_enable_resources,
342 #if CONFIG(HAVE_ACPI_TABLES)
343 .write_acpi_tables = acpi_write_hpet,
344 #endif
345 .init = lpc_init,
346 .final = lpc_final,
347 .scan_bus = scan_static_bus,
348 .ops_pci = &pci_dev_ops_pci,
349 .acpi_name = lpc_acpi_name,
350 };
351
352 static const unsigned short pci_device_ids[] = {
353 /* PCI device ID is used on all discrete FCHs and Family 16h Models 00h-3Fh */
354 PCI_DID_AMD_SB900_LPC,
355 /* PCI device ID is used on all integrated FCHs except Family 16h Models 00h-3Fh */
356 PCI_DID_AMD_CZ_LPC,
357 0
358 };
359 static const struct pci_driver lpc_driver __pci_driver = {
360 .ops = &lpc_ops,
361 .vendor = PCI_VID_AMD,
362 .devices = pci_device_ids,
363 };
364