1/* SPDX-License-Identifier: GPL-2.0-only */ 2 3/* Intel Cougar Point PCH support */ 4#include <southbridge/intel/bd82x6x/pch.h> 5 6Scope(\) 7{ 8 // PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l) 9 OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80) 10 Field(PMIO, ByteAcc, NoLock, Preserve) 11 { 12 Offset(0x20), // GPE0_STS 13 , 16, 14 GS00, 1, // GPIO00 SCI/Wake Status 15 GS01, 1, // GPIO01 SCI/Wake Status 16 GS02, 1, // GPIO02 SCI/Wake Status 17 GS03, 1, // GPIO03 SCI/Wake Status 18 GS04, 1, // GPIO04 SCI/Wake Status 19 GS05, 1, // GPIO05 SCI/Wake Status 20 GS06, 1, // GPIO06 SCI/Wake Status 21 GS07, 1, // GPIO07 SCI/Wake Status 22 GS08, 1, // GPIO08 SCI/Wake Status 23 GS09, 1, // GPIO09 SCI/Wake Status 24 GS10, 1, // GPIO10 SCI/Wake Status 25 GS11, 1, // GPIO11 SCI/Wake Status 26 GS12, 1, // GPIO12 SCI/Wake Status 27 GS13, 1, // GPIO13 SCI/Wake Status 28 GS14, 1, // GPIO14 SCI/Wake Status 29 GS15, 1, // GPIO15 SCI/Wake Status 30 Offset(0x28), // GPE0_EN 31 , 16, 32 GE00, 1, // GPIO00 SCI/Wake Enable 33 GE01, 1, // GPIO01 SCI/Wake Enable 34 GE02, 1, // GPIO02 SCI/Wake Enable 35 GE03, 1, // GPIO03 SCI/Wake Enable 36 GE04, 1, // GPIO04 SCI/Wake Enable 37 GE05, 1, // GPIO05 SCI/Wake Enable 38 GE06, 1, // GPIO06 SCI/Wake Enable 39 GE07, 1, // GPIO07 SCI/Wake Enable 40 GE08, 1, // GPIO08 SCI/Wake Enable 41 GE09, 1, // GPIO09 SCI/Wake Enable 42 GE10, 1, // GPIO10 SCI/Wake Enable 43 GE11, 1, // GPIO11 SCI/Wake Enable 44 GE12, 1, // GPIO12 SCI/Wake Enable 45 GE13, 1, // GPIO13 SCI/Wake Enable 46 GE14, 1, // GPIO14 SCI/Wake Enable 47 GE15, 1, // GPIO15 SCI/Wake Enable 48 Offset(0x42), // General Purpose Control 49 , 1, // skip 1 bit 50 GPEC, 1, // SWGPE_CTRL 51 } 52 53 // GPIO IO mapped registers (0x1f.0 reg 0x48.l) 54 OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c) 55 Field(GPIO, ByteAcc, NoLock, Preserve) 56 { 57 Offset(0x0c), // GPIO Level 58 GP00, 1, 59 GP01, 1, 60 GP02, 1, 61 GP03, 1, 62 GP04, 1, 63 GP05, 1, 64 GP06, 1, 65 GP07, 1, 66 GP08, 1, 67 GP09, 1, 68 GP10, 1, 69 GP11, 1, 70 GP12, 1, 71 GP13, 1, 72 GP14, 1, 73 GP15, 1, 74 GP16, 1, 75 GP17, 1, 76 GP18, 1, 77 GP19, 1, 78 GP20, 1, 79 GP21, 1, 80 GP22, 1, 81 GP23, 1, 82 GP24, 1, 83 GP25, 1, 84 GP26, 1, 85 GP27, 1, 86 GP28, 1, 87 GP29, 1, 88 GP30, 1, 89 GP31, 1, 90 Offset(0x18), // GPIO Blink 91 GB00, 1, 92 GB01, 1, 93 GB02, 1, 94 GB03, 1, 95 GB04, 1, 96 GB05, 1, 97 GB06, 1, 98 GB07, 1, 99 GB08, 1, 100 GB09, 1, 101 GB10, 1, 102 GB11, 1, 103 GB12, 1, 104 GB13, 1, 105 GB14, 1, 106 GB15, 1, 107 GB16, 1, 108 GB17, 1, 109 GB18, 1, 110 GB19, 1, 111 GB20, 1, 112 GB21, 1, 113 GB22, 1, 114 GB23, 1, 115 GB24, 1, 116 GB25, 1, 117 GB26, 1, 118 GB27, 1, 119 GB28, 1, 120 GB29, 1, 121 GB30, 1, 122 GB31, 1, 123 Offset(0x2c), // GPIO Invert 124 GIV0, 8, 125 GIV1, 8, 126 GIV2, 8, 127 GIV3, 8, 128 Offset(0x38), // GPIO Level 2 129 GP32, 1, 130 GP33, 1, 131 GP34, 1, 132 GP35, 1, 133 GP36, 1, 134 GP37, 1, 135 GP38, 1, 136 GP39, 1, 137 GP40, 1, 138 GP41, 1, 139 GP42, 1, 140 GP43, 1, 141 GP44, 1, 142 GP45, 1, 143 GP46, 1, 144 GP47, 1, 145 GP48, 1, 146 GP49, 1, 147 GP50, 1, 148 GP51, 1, 149 GP52, 1, 150 GP53, 1, 151 GP54, 1, 152 GP55, 1, 153 GP56, 1, 154 GP57, 1, 155 GP58, 1, 156 GP59, 1, 157 GP60, 1, 158 GP61, 1, 159 GP62, 1, 160 GP63, 1, 161 Offset(0x48), // GPIO Level 3 162 GP64, 1, 163 GP65, 1, 164 GP66, 1, 165 GP67, 1, 166 GP68, 1, 167 GP69, 1, 168 GP70, 1, 169 GP71, 1, 170 GP72, 1, 171 GP73, 1, 172 GP74, 1, 173 GP75, 1, 174 } 175 176 177 // ICH7 Root Complex Register Block. Memory Mapped through RCBA) 178 OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) 179 Field(RCRB, DWordAcc, Lock, Preserve) 180 { 181 Offset(0x0000), // Backbone 182 Offset(0x1000), // Chipset 183 Offset(0x3000), // Legacy Configuration Registers 184 Offset(0x3404), // High Performance Timer Configuration 185 HPAS, 2, // Address Select 186 , 5, 187 HPTE, 1, // Address Enable 188 Offset(0x3418), // FD (Function Disable) 189 , 1, // Reserved 190 PCID, 1, // PCI bridge disable 191 SA1D, 1, // SATA1 disable 192 SMBD, 1, // SMBUS disable 193 HDAD, 1, // Azalia disable 194 , 8, // Reserved 195 EH2D, 1, // EHCI #2 disable 196 LPBD, 1, // LPC bridge disable 197 EH1D, 1, // EHCI #1 disable 198 RP1D, 1, // Root Port 1 disable 199 RP2D, 1, // Root Port 2 disable 200 RP3D, 1, // Root Port 3 disable 201 RP4D, 1, // Root Port 4 disable 202 RP5D, 1, // Root Port 5 disable 203 RP6D, 1, // Root Port 6 disable 204 RP7D, 1, // Root Port 7 disable 205 RP8D, 1, // Root Port 8 disable 206 TTRD, 1, // Thermal sensor registers disable 207 SA2D, 1, // SATA2 disable 208 Offset(0x3428), // FD2 (Function Disable 2) 209 BDFD, 1, // Display BDF 210 ME1D, 1, // ME Interface 1 disable 211 ME2D, 1, // ME Interface 2 disable 212 IDRD, 1, // IDE redirect disable 213 KTCT, 1, // Keyboard Text redirect disable 214 } 215} 216 217// High Definition Audio (Azalia) 0:1b.0 218#include "audio.asl" 219 220// PCI Express Ports 0:1c.x 221#include <southbridge/intel/common/acpi/pcie.asl> 222 223// USB EHCI 0:1d.0 and 0:1a.0, XHCI 0:14.0 224#include "usb.asl" 225 226// LPC Bridge 0:1f.0 227#include "lpc.asl" 228 229// SATA 0:1f.2, 0:1f.5 230#include "sata.asl" 231 232// SMBus 0:1f.3 233#include <southbridge/intel/common/acpi/smbus.asl> 234 235Method (_OSC, 4) 236{ 237 /* 238 * Arg0 - A Buffer containing a UUID 239 * Arg1 - An Integer containing a Revision ID of the buffer format 240 * Arg2 - An Integer containing a count of entries in Arg3 241 * Arg3 - A Buffer containing a list of DWORD capabilities 242 */ 243 /* Check for XHCI */ 244 If (Arg0 == ToUUID("7c9512a9-1705-4cb4-af7d-506a2423ab71")) 245 { 246 Return (^XHC.POSC(Arg2, Arg3)) 247 } 248 249 /* Check for PCIe */ 250 If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) 251 { 252 /* Let OS control everything */ 253 Return (Arg3) 254 } 255 256 /* Else Return Unrecognized UUID */ 257 CreateDWordField (Arg3, 0, CDW1) 258 CDW1 |= 4 259 Return (Arg3) 260 261} 262