1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include <device/pci_ops.h>
8 #include <device/mmio.h>
9 #include <delay.h>
10 #include <device/azalia_device.h>
11
12 #include "chip.h"
13 #include "pch.h"
14
codec_detect(u8 * base)15 static int codec_detect(u8 *base)
16 {
17 u8 reg8;
18
19 if (azalia_exit_reset(base) < 0)
20 goto no_codec;
21
22 /* Write back the value once reset bit is set. */
23 write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG));
24
25 /* Read in Codec location (BAR + 0xe)[2..0] */
26 reg8 = read8(base + HDA_STATESTS_REG);
27 reg8 &= 0x0f;
28 if (!reg8)
29 goto no_codec;
30
31 return reg8;
32
33 no_codec:
34 /* Codec not found, put HDA back in reset */
35 azalia_enter_reset(base);
36 printk(BIOS_DEBUG, "Azalia: No codec!\n");
37 return 0;
38 }
39
azalia_init(struct device * dev)40 static void azalia_init(struct device *dev)
41 {
42 u8 *base;
43 struct resource *res;
44 u32 codec_mask;
45 u32 reg32;
46
47 res = probe_resource(dev, PCI_BASE_ADDRESS_0);
48 if (!res)
49 return;
50
51 // NOTE this will break as soon as the Azalia gets a bar above 4G.
52 // Is there anything we can do about it?
53 base = res2mmio(res, 0, 0);
54 printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
55
56 if (RCBA32(CIR31) & (1 << 31)) {
57 reg32 = pci_read_config32(dev, 0x120);
58 reg32 &= 0xf8ffff01;
59 reg32 |= (1 << 24); // 2 << 24 for server
60 reg32 |= RCBA32(CIR31) & 0xfe;
61 pci_write_config32(dev, 0x120, reg32);
62
63 pci_or_config16(dev, 0x78, 1 << 11);
64 } else
65 printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n");
66
67 pci_and_config32(dev, 0x114, ~0xfe);
68
69 // Set VCi enable bit
70 pci_or_config32(dev, 0x120, 1 << 31);
71
72 // Enable HDMI codec:
73 pci_or_config32(dev, 0xc4, 1 << 1);
74
75 pci_or_config8(dev, 0x43, 1 << 6);
76
77 /* Additional programming steps */
78 pci_or_config32(dev, 0xc4, 1 << 13);
79
80 pci_or_config32(dev, 0xc4, 1 << 10);
81
82 pci_and_config32(dev, 0xd0, ~(1 << 31));
83
84 if (dev->device == 0x1e20) {
85 /* Additional step on Panther Point */
86 pci_or_config32(dev, 0xc4, 1 << 17);
87 }
88
89 /* Set Bus Master */
90 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
91
92 pci_write_config8(dev, 0x3c, 0x0a); // unused?
93
94 /* Codec Initialization Programming Sequence */
95
96 /* Take controller out of reset */
97 reg32 = read32(base + HDA_GCTL_REG);
98 reg32 |= HDA_GCTL_CRST;
99 write32(base + HDA_GCTL_REG, reg32);
100 /* Wait 1ms */
101 udelay(1000);
102
103 // Select Azalia mode. This needs to be controlled via devicetree.cb
104 pci_or_config8(dev, 0x40, 1); // Audio Control
105
106 // Docking not supported
107 pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status
108
109 codec_mask = codec_detect(base);
110
111 if (codec_mask) {
112 printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
113 azalia_codecs_init(base, codec_mask);
114 }
115
116 /* Enable dynamic clock gating */
117 pci_update_config8(dev, 0x43, ~0x07, (1 << 2) | (1 << 0));
118 }
119
azalia_acpi_name(const struct device * dev)120 static const char *azalia_acpi_name(const struct device *dev)
121 {
122 return "HDEF";
123 }
124
125 struct device_operations bd82x6x_azalia_ops = {
126 .read_resources = pci_dev_read_resources,
127 .set_resources = pci_dev_set_resources,
128 .enable_resources = pci_dev_enable_resources,
129 .init = azalia_init,
130 .ops_pci = &pci_dev_ops_pci,
131 .acpi_name = azalia_acpi_name,
132 };
133