1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <arch/bootblock.h> 4 #include <device/pci_ops.h> 5 #include <southbridge/intel/common/early_spi.h> 6 #include "pch.h" 7 setup_port80(void)8static void setup_port80(void) 9 { 10 /* Enable port 80 POST */ 11 if (CONFIG(POST_DEVICE_PCI_PCIE)) 12 RCBA32(GCS) |= 0x04; /* ... on PCI(e) */ 13 else 14 RCBA32(GCS) &= (~0x04); /* ... on LPC */ 15 } 16 set_spi_speed(void)17static void set_spi_speed(void) 18 { 19 u32 fdod; 20 u8 ssfc; 21 22 /* Observe SPI Descriptor Component Section 0 */ 23 RCBA32(0x38b0) = 0x1000; 24 25 /* Extract the Write/Erase SPI Frequency from descriptor */ 26 fdod = RCBA32(0x38b4); 27 fdod >>= 24; 28 fdod &= 7; 29 30 /* Set Software Sequence frequency to match */ 31 ssfc = RCBA8(0x3893); 32 ssfc &= ~7; 33 ssfc |= fdod; 34 RCBA8(0x3893) = ssfc; 35 } 36 bootblock_early_southbridge_init(void)37void bootblock_early_southbridge_init(void) 38 { 39 enable_spi_prefetching_and_caching(); 40 41 early_pch_init(); 42 43 setup_port80(); 44 set_spi_speed(); 45 46 /* Enable upper 128bytes of CMOS */ 47 RCBA32(RC) = (1 << 2); 48 } 49