1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <device/mmio.h>
4 #include <device/pci_ops.h>
5 #include "pch.h"
6 #include "cpu/intel/model_206ax/model_206ax.h"
7 #include <cpu/x86/msr.h>
8
9 /* Temporary address for the thermal BAR */
10 #define TBARB_TEMP 0x40000000
11
12 /* Early thermal init, must be done prior to giving ME its memory
13 which is done at the end of raminit */
early_thermal_init(void)14 void early_thermal_init(void)
15 {
16 const pci_devfn_t dev = PCH_THERMAL_DEV;
17
18 /* Program address for temporary BAR */
19 pci_write_config32(dev, 0x40, TBARB_TEMP);
20 pci_write_config32(dev, 0x44, 0x0);
21
22 /* Activate temporary BAR */
23 pci_or_config32(dev, 0x40, 5);
24
25 write16p(TBARB_TEMP + 0x04, 0x3a2b);
26
27 write8p(TBARB_TEMP + 0x0c, 0xff);
28 write8p(TBARB_TEMP + 0x0d, 0x00);
29 write8p(TBARB_TEMP + 0x0e, 0x40);
30 write8p(TBARB_TEMP + 0x82, 0x00);
31 write8p(TBARB_TEMP + 0x01, 0xba);
32
33 /* Perform init */
34 /* Configure TJmax */
35 const msr_t msr = rdmsr(MSR_TEMPERATURE_TARGET);
36 write16p(TBARB_TEMP + 0x12, ((msr.lo >> 16) & 0xff) << 6);
37 /* Northbridge temperature slope and offset */
38 write16p(TBARB_TEMP + 0x16, 0x808c);
39
40 write16p(TBARB_TEMP + 0x14, 0xde87);
41
42 /* Enable thermal data reporting, processor, PCH and northbridge */
43 write16p(TBARB_TEMP + 0x1a, (read16p(TBARB_TEMP + 0x1a) & ~0xf) | 0x10f0);
44
45 /* Disable temporary BAR */
46 pci_and_config32(dev, 0x40, ~1);
47
48 pci_write_config32(dev, 0x40, 0);
49
50 RCBA32_AND_OR(0x38b0, 0xffff8003, 0x403c);
51 }
52