1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include <device/mmio.h>
5 #include <device/pci_ops.h>
6 #include <device/pci_def.h>
7 #include <southbridge/intel/common/rcba.h>
8 #include <southbridge/intel/common/pmbase.h>
9
10 #include "pch.h"
11 #include "chip.h"
12
early_usb_init(void)13 void early_usb_init(void)
14 {
15 u32 reg32;
16 const u32 rcba_dump[8] = {
17 /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050,
18 /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630,
19 };
20 /* Care should be taken to limit this array to not more than 80 (0x50) entries.
21 * See below. */
22 const u32 currents[] = { USBIR_TXRX_GAIN_MOBILE_LOW, USBIR_TXRX_GAIN_DEFAULT,
23 USBIR_TXRX_GAIN_HIGH, 0x20000f51, 0x2000094a, 0x2000035f,
24 USBIR_TXRX_GAIN_DESKTOP6_LOW, USBIR_TXRX_GAIN_DESKTOP6_HIGH,
25 USBIR_TXRX_GAIN_DESKTOP7_LOW, USBIR_TXRX_GAIN_DESKTOP7_MED,
26 0x20000053, 0x2000055f, 0x20000f5f};
27 const struct device *dev = pcidev_on_root(0x1d, 0);
28 const struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
29 const struct southbridge_usb_port *portmap = config->usb_port_config;
30 int i;
31
32 /* Unlock registers. */
33 write_pmbase16(UPRWC, read_pmbase16(UPRWC) | UPRWC_WR_EN);
34
35 for (i = 0; i < 14; i++) {
36 /*
37 * If the value from devicetree is beyond the highest possible current map
38 * index, it is meant to go directly into (bottom 12 bits of) USBIRx.
39 */
40 if (portmap[i].current >= ARRAY_SIZE(currents)) {
41 RCBA32(USBIR0 + 4 * i) = 0x20000000 | (portmap[i].current & 0xfff);
42 continue;
43 }
44 if (portmap[i].enabled && !pch_is_mobile() &&
45 currents[portmap[i].current] == USBIR_TXRX_GAIN_MOBILE_LOW) {
46 /*
47 * Note for developers: You can fix this by re-running autoport on
48 * vendor firmware and then updating portmap currents accordingly.
49 * If that is not possible, another option is to choose a non-zero
50 * current setting. In either case, please test all the USB ports.
51 */
52 printk(BIOS_ERR, "%s: USB%02d: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!\n",
53 __func__, i);
54
55 RCBA32(USBIR0 + 4 * i) = USBIR_TXRX_GAIN_DEFAULT;
56 } else {
57 RCBA32(USBIR0 + 4 * i) = currents[portmap[i].current];
58 }
59 }
60 for (i = 0; i < 10; i++)
61 RCBA32(0x3538 + 4 * i) = 0;
62
63 for (i = 0; i < 8; i++)
64 RCBA32(0x3560 + 4 * i) = rcba_dump[i];
65 for (i = 0; i < 8; i++)
66 RCBA32(0x3580 + 4 * i) = 0;
67 reg32 = 0;
68 for (i = 0; i < 14; i++)
69 if (!portmap[i].enabled)
70 reg32 |= (1 << i);
71 RCBA32(USBPDO) = reg32;
72 reg32 = 0;
73 for (i = 0; i < 8; i++)
74 if (portmap[i].enabled && portmap[i].oc_pin >= 0)
75 reg32 |= (1 << (i + 8 * portmap[i].oc_pin));
76 RCBA32(USBOCM1) = reg32;
77 reg32 = 0;
78 for (i = 8; i < 14; i++)
79 if (portmap[i].enabled && portmap[i].oc_pin >= 4)
80 reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4)));
81 RCBA32(USBOCM2) = reg32;
82 for (i = 0; i < 22; i++)
83 RCBA32(0x35a8 + 4 * i) = 0;
84
85 pci_write_config32(PCH_XHCI_DEV, 0xe4, 0x00000000);
86
87 /* Relock registers. */
88 write_pmbase16(UPRWC, 0);
89 }
90