1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ops.h>
7 #include <device/pciexp.h>
8 #include <device/pci_ids.h>
9 #include <southbridge/intel/common/pciehp.h>
10 #include <assert.h>
11
12 #include "chip.h"
13 #include "pch.h"
14
pch_pcie_acpi_name(const struct device * dev)15 static const char *pch_pcie_acpi_name(const struct device *dev)
16 {
17 ASSERT(dev);
18
19 if (PCI_SLOT(dev->path.pci.devfn) == 0x1c) {
20 static const char *names[] = { "RP01",
21 "RP02",
22 "RP03",
23 "RP04",
24 "RP05",
25 "RP06",
26 "RP07",
27 "RP08"};
28
29 return names[PCI_FUNC(dev->path.pci.devfn)];
30 }
31
32 return NULL;
33 }
34
pci_is_hotplugable(struct device * dev)35 static bool pci_is_hotplugable(struct device *dev)
36 {
37 struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
38
39 return config && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)];
40 }
41
pch_pcie_pm_early(struct device * dev)42 static void pch_pcie_pm_early(struct device *dev)
43 {
44 u16 link_width_p0, link_width_p4;
45 struct device *child = NULL;
46 u8 slot_power_limit = 10; /* 10W for x1 */
47 static u8 slot_number = 1;
48 u32 reg32, cap;
49 u8 reg8;
50
51 reg32 = RCBA32(RPC);
52
53 /* Port 0-3 link aggregation from PCIEPCS1[1:0] soft strap */
54 switch (reg32 & 3) {
55 case 3:
56 link_width_p0 = 4;
57 break;
58 case 1:
59 case 2:
60 link_width_p0 = 2;
61 break;
62 case 0:
63 default:
64 link_width_p0 = 1;
65 }
66
67 /* Port 4-7 link aggregation from PCIEPCS2[1:0] soft strap */
68 switch ((reg32 >> 2) & 3) {
69 case 3:
70 link_width_p4 = 4;
71 break;
72 case 1:
73 case 2:
74 link_width_p4 = 2;
75 break;
76 case 0:
77 default:
78 link_width_p4 = 1;
79 }
80
81 /* Enable dynamic clock gating where needed */
82 reg8 = pci_read_config8(dev, 0xe1);
83 switch (PCI_FUNC(dev->path.pci.devfn)) {
84 case 0: /* Port 0 */
85 if (link_width_p0 == 4)
86 slot_power_limit = 40; /* 40W for x4 */
87 else if (link_width_p0 == 2)
88 slot_power_limit = 20; /* 20W for x2 */
89 reg8 |= 0x3f;
90 break;
91 case 4: /* Port 4 */
92 if (link_width_p4 == 4)
93 slot_power_limit = 40; /* 40W for x4 */
94 else if (link_width_p4 == 2)
95 slot_power_limit = 20; /* 20W for x2 */
96 reg8 |= 0x3f;
97 break;
98 case 1: /* Port 1 only if Port 0 is x1 */
99 if (link_width_p0 == 1)
100 reg8 |= 0x3;
101 break;
102 case 2: /* Port 2 only if Port 0 is x1 or x2 */
103 case 3: /* Port 3 only if Port 0 is x1 or x2 */
104 if (link_width_p0 <= 2)
105 reg8 |= 0x3;
106 break;
107 case 5: /* Port 5 only if Port 4 is x1 */
108 if (link_width_p4 == 1)
109 reg8 |= 0x3;
110 break;
111 case 6: /* Port 7 only if Port 4 is x1 or x2 */
112 case 7: /* Port 7 only if Port 4 is x1 or x2 */
113 if (link_width_p4 <= 2)
114 reg8 |= 0x3;
115 break;
116 }
117 pci_write_config8(dev, 0xe1, reg8);
118
119 /* Set 0xE8[0] = 1 */
120 pci_or_config32(dev, 0xe8, 1);
121
122 /* Adjust Common Clock exit latency */
123 reg32 = pci_read_config32(dev, 0xd8);
124 reg32 &= ~(1 << 17);
125 reg32 |= (1 << 16) | (1 << 15);
126 reg32 &= ~(1 << 31); /* Disable PME# SCI for native PME handling */
127 pci_write_config32(dev, 0xd8, reg32);
128
129 cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
130
131 /* Adjust ASPM L1 exit latency */
132 reg32 = pci_read_config32(dev, cap + PCI_EXP_LNKCAP);
133 reg32 &= ~PCI_EXP_LNKCAP_L1EL;
134 if (RCBA32(CIR9) & (1 << 16)) {
135 /* If RCBA+2320[15]=1 set ASPM L1 to 8-16us */
136 reg32 |= (4 << 15);
137 } else {
138 /* Else set ASPM L1 to 2-4us */
139 reg32 |= (2 << 15);
140 }
141 pci_write_config32(dev, cap + PCI_EXP_LNKCAP, reg32);
142
143 /*
144 * PCI device enumeration hasn't started yet, thus any downstream device here
145 * must be a static device from devicetree.cb.
146 * If one is found assume it's an integrated device and not a PCIe slot.
147 */
148 if (dev->downstream)
149 child = pcidev_path_behind(dev->downstream, PCI_DEVFN(0, 0));
150
151 /* Set slot power limit as configured above */
152 reg32 = pci_read_config32(dev, cap + PCI_EXP_SLTCAP);
153 if (pci_is_hotplugable(dev))
154 reg32 |= (PCI_EXP_SLTCAP_HPS | PCI_EXP_SLTCAP_HPC);
155 else
156 reg32 &= ~(PCI_EXP_SLTCAP_HPS | PCI_EXP_SLTCAP_HPC);
157 reg32 &= ~PCI_EXP_SLTCAP_SPLS; /* 16:15 = Slot power scale */
158 reg32 &= ~PCI_EXP_SLTCAP_SPLV; /* 14:7 = Slot power limit */
159 reg32 &= ~PCI_EXP_SLTCAP_PSN;
160 if (!child || !child->on_mainboard) {
161 /* Only PCIe slots have a power limit and slot number */
162 reg32 |= (slot_power_limit << 7);
163 reg32 |= (slot_number++ << 19);
164 }
165 pci_write_config32(dev, cap + PCI_EXP_SLTCAP, reg32);
166 }
167
pch_pcie_pm_late(struct device * dev)168 static void pch_pcie_pm_late(struct device *dev)
169 {
170 struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
171 enum aspm_type apmc = 0;
172
173 /* Set 0x314 = 0x743a361b */
174 pci_write_config32(dev, 0x314, 0x743a361b);
175
176 /* Set 0x318[31:16] = 0x1414 */
177 pci_update_config32(dev, 0x318, 0x0000ffff, 0x14140000);
178
179 /* Set 0x324[5] = 1 */
180 pci_or_config32(dev, 0x324, 1 << 5);
181
182 /* Set 0x330[7:0] = 0x40 */
183 pci_update_config32(dev, 0x330, ~0xff, 0x40);
184
185 /* Set 0x33C[24:0] = 0x854c74 */
186 pci_update_config32(dev, 0x33c, 0xff000000, 0x00854c74);
187
188 /* No IO-APIC, Disable EOI forwarding */
189 pci_or_config32(dev, 0xd4, 1 << 1);
190
191 /* Check for a rootport ASPM override */
192 apmc = config->pcie_aspm[PCI_FUNC(dev->path.pci.devfn)];
193
194 /* Setup the override or get the real ASPM setting */
195 if (apmc) {
196 pci_or_config32(dev, 0xd4, (apmc << 2) | (1 << 4));
197
198 } else {
199 apmc = pci_read_config32(dev, 0x50) & 3;
200 }
201
202 /* If both L0s and L1 enabled then set root port 0xE8[1]=1 */
203 if (apmc == PCIE_ASPM_BOTH)
204 pci_or_config32(dev, 0xe8, 1 << 1);
205 }
206
pci_init(struct device * dev)207 static void pci_init(struct device *dev)
208 {
209 u16 reg16;
210
211 printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
212
213 /* Enable Bus Master */
214 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
215
216 /* Set Cache Line Size to 0x10 */
217 // This has no effect but the OS might expect it
218 pci_write_config8(dev, 0x0c, 0x10);
219
220 pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY);
221
222 /* Clear errors in status registers. FIXME: Do something? */
223 reg16 = pci_read_config16(dev, 0x06);
224 //reg16 |= 0xf900;
225 pci_write_config16(dev, 0x06, reg16);
226
227 reg16 = pci_read_config16(dev, 0x1e);
228 //reg16 |= 0xf900;
229 pci_write_config16(dev, 0x1e, reg16);
230
231 /* Enable expresscard hotplug events. */
232 if (pci_is_hotplugable(dev))
233 pci_or_config32(dev, 0xd8, 1 << 30);
234 }
235
pch_pcie_enable(struct device * dev)236 static void pch_pcie_enable(struct device *dev)
237 {
238 /* Power Management init before enumeration */
239 pch_pcie_pm_early(dev);
240 }
241
pch_pciexp_scan_bridge(struct device * dev)242 static void pch_pciexp_scan_bridge(struct device *dev)
243 {
244 uint32_t cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
245
246 if (CONFIG(PCIEXP_HOTPLUG) && pci_is_hotplugable(dev)) {
247 pciexp_hotplug_scan_bridge(dev);
248 } else {
249 /* Normal PCIe Scan */
250 pciexp_scan_bridge(dev);
251 }
252 if ((pci_read_config16(dev, cap + PCI_EXP_SLTSTA) & PCI_EXP_SLTSTA_PDS) &&
253 !dev_is_active_bridge(dev))
254 printk(BIOS_WARNING, "%s: Has a slow downstream device. Enumeration failed.\n",
255 dev_path(dev));
256
257 /* Late Power Management init after bridge device enumeration */
258 pch_pcie_pm_late(dev);
259 }
260
261 struct device_operations bd82x6x_pcie_rp_ops = {
262 .read_resources = pci_bus_read_resources,
263 .set_resources = pci_dev_set_resources,
264 .enable_resources = pci_bus_enable_resources,
265 .init = pci_init,
266 .enable = pch_pcie_enable,
267 .scan_bus = pch_pciexp_scan_bridge,
268 .acpi_name = pch_pcie_acpi_name,
269 .ops_pci = &pci_dev_ops_pci,
270 };
271