1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include <device/pci_ops.h>
5 #include <southbridge/intel/common/pmbase.h>
6 #include <southbridge/intel/common/pmutil.h>
7 #include <southbridge/intel/common/rcba.h>
8 #include <spi-generic.h>
9
10 #include "finalize.h"
11
intel_pch_finalize_smm(void)12 void intel_pch_finalize_smm(void)
13 {
14 const pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0);
15
16 /* Lock SPIBAR */
17 RCBA32_OR(0x3804, (1 << 15));
18
19 if (CONFIG(SPI_FLASH_SMM))
20 /* Re-init SPI driver to handle locked BAR */
21 spi_init();
22
23 /* TCLOCKDN: TC Lockdown */
24 RCBA32_OR(0x0050, (1UL << 31));
25
26 /* BIOS Interface Lockdown */
27 RCBA32_OR(0x3410, (1 << 0));
28
29 /* Function Disable SUS Well Lockdown */
30 RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
31
32 pci_or_config16(lpc_dev, D31F0_GEN_PMCON_1, SMI_LOCK);
33
34 pci_or_config8(lpc_dev, D31F0_GEN_PMCON_LOCK,
35 ACPI_BASE_LOCK | SLP_STR_POL_LOCK);
36
37 pci_update_config32(lpc_dev, D31F0_ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK);
38
39 if (CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT))
40 /* PMSYNC */
41 RCBA32_OR(0x33c4, (1UL << 31));
42
43 /* R/WO registers */
44 RCBA32(0x21a4) = RCBA32(0x21a4);
45 pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
46 pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
47
48 if (CONFIG(BOOTMEDIA_SMM_BWP))
49 write_pmbase16(SMI_EN, read_pmbase16(SMI_EN) | TCO_EN);
50
51 write_pmbase16(TCO1_CNT, read_pmbase16(TCO1_CNT) | TCO_LOCK);
52
53 post_code(POSTCODE_OS_BOOT);
54 }
55