1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <stdint.h>
4 #include <arch/bootblock.h>
5 #include <device/pci_ops.h>
6 #include <device/pci_ids.h>
7 #include <device/pci_type.h>
8 #include "i82371eb.h"
9
10 #define PCI_ID(VENDOR_ID, DEVICE_ID) \
11 ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
12
pci_locate_device(unsigned int pci_id,pci_devfn_t dev)13 static pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev)
14 {
15 for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
16 unsigned int id;
17 id = pci_read_config32(dev, 0);
18 if (id == pci_id)
19 return dev;
20 }
21 return PCI_DEV_INVALID;
22 }
23
24 /* TODO: Does not need to happen before console init. */
25 /* The whole rom is not accessible before this so limit
26 the bootblock size. */
27 #if CONFIG_C_ENV_BOOTBLOCK_SIZE > 0x10000
28 #error "CONFIG_C_ENV_BOOTBLOCK_SIZE needs to be below 64KiB"
29 #endif
bootblock_early_southbridge_init(void)30 void bootblock_early_southbridge_init(void)
31 {
32 u16 reg16;
33
34 /*
35 * Note: The Intel 82371AB/EB/MB ISA device can be on different
36 * PCI bus:device.function locations on different boards.
37 * Examples we encountered: 00:07.0, 00:04.0, or 00:14.0.
38 * But scanning for the PCI IDs (instead of hardcoding
39 * bus/device/function numbers) works on all boards.
40 */
41 const pci_devfn_t dev = pci_locate_device(PCI_ID(PCI_VID_INTEL,
42 PCI_DID_INTEL_82371AB_ISA), 0);
43
44 /* Enable access to the whole ROM, disable ROM write access. */
45 reg16 = pci_read_config16(dev, XBCS);
46 reg16 |= LOWER_BIOS_ENABLE | EXT_BIOS_ENABLE | EXT_BIOS_ENABLE_1MB;
47 reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */
48 pci_write_config16(dev, XBCS, reg16);
49
50 /* Enable (RTC and) upper NVRAM bank. */
51 pci_write_config8(dev, RTCCFG, RTC_POS_DECODE | UPPER_RAM_EN | RTC_ENABLE);
52 }
53