1/* SPDX-License-Identifier: GPL-2.0-only */ 2 3/* Intel 82801Gx support */ 4 5#include "../i82801gx.h" 6 7Scope(\) 8{ 9 // IO-Trap at 0x800. This is the ACPI->SMI communication interface. 10 11 OperationRegion(IO_T, SystemIO, 0x800, 0x10) 12 Field(IO_T, ByteAcc, NoLock, Preserve) 13 { 14 Offset(0x8), 15 TRP0, 8 // IO-Trap at 0x808 16 } 17 18 /* SMI I/O Trap */ 19 Method(TRAP, 1, Serialized) 20 { 21 SMIF = Arg0 // SMI Function 22 TRP0 = 0 // Generate trap 23 Return (SMIF) // Return value of SMI handler 24 } 25 26 // ICH7 Power Management Registers, located at PMBASE (0x1f.0 0x40.l) 27 OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80) 28 Field(PMIO, ByteAcc, NoLock, Preserve) 29 { 30 Offset(0x42), // General Purpose Control 31 , 1, // skip 1 bit 32 GPEC, 1, // TCO status 33 , 9, // skip 9 more bits 34 SCIS, 1, // TCO DMI status 35 , 6 // To the end of the word 36 } 37 38 // ICH7 GPIO IO mapped registers (0x1f.0 reg 0x48.l) 39 OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c) 40 Field(GPIO, ByteAcc, NoLock, Preserve) 41 { 42 // GPIO Use Select 43 GU00, 8, 44 GU01, 8, 45 GU02, 8, 46 GU03, 8, 47 // GPIO IO Select 48 GIO0, 8, 49 GIO1, 8, 50 GIO2, 8, 51 GIO3, 8, 52 Offset(0x0c), // GPIO Level 53 GP00, 1, 54 GP01, 1, 55 GP02, 1, 56 GP03, 1, 57 GP04, 1, 58 GP05, 1, 59 GP06, 1, 60 GP07, 1, 61 GP08, 1, 62 GP09, 1, 63 GP10, 1, 64 GP11, 1, 65 GP12, 1, 66 GP13, 1, 67 GP14, 1, 68 GP15, 1, 69 GP16, 1, 70 GP17, 1, 71 GP18, 1, 72 GP19, 1, 73 GP20, 1, 74 GP21, 1, 75 GP22, 1, 76 GP23, 1, 77 GP24, 1, 78 GP25, 1, 79 GP26, 1, 80 GP27, 1, 81 GP28, 1, 82 GP29, 1, 83 GP30, 1, 84 GP31, 1, 85 Offset(0x18), // GPIO Blink 86 GB00, 8, 87 GB01, 8, 88 GB02, 8, 89 GB03, 8, 90 Offset(0x2c), // GPIO Invert 91 GIV0, 8, 92 GIV1, 8, 93 GIV2, 8, 94 GIV3, 8, 95 // GPIO Use Select 2 96 GU04, 8, 97 GU05, 8, 98 GU06, 8, 99 GU07, 8, 100 // GPIO IO Select 2 101 GIO4, 8, 102 GIO5, 8, 103 GIO6, 8, 104 GIO7, 8, 105 // GPIO Level 2 106 GP32, 1, 107 GP33, 1, 108 GP34, 1, 109 GP35, 1, 110 GP36, 1, 111 GP37, 1, 112 GP38, 1, 113 GP39, 1, 114 GL05, 8, 115 GL06, 8, 116 GL07, 8 117 } 118 119 120 // ICH7 Root Complex Register Block. Memory Mapped through RCBA) 121 OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) 122 Field(RCRB, DWordAcc, Lock, Preserve) 123 { 124 // Backbone 125 Offset(0x1000), // Chipset 126 Offset(0x3000), // Legacy Configuration Registers 127 Offset(0x3404), // High Performance Timer Configuration 128 HPAS, 2, // Address Select 129 , 5, 130 HPTE, 1, // Address Enable 131 Offset(0x3418), // FD (Function Disable) 132 , 1, // Reserved 133 PATD, 1, // PATA disable 134 SATD, 1, // SATA disable 135 SMBD, 1, // SMBUS disable 136 HDAD, 1, // Azalia disable 137 A97D, 1, // AC'97 disable 138 M97D, 1, // AC'97 disable 139 ILND, 1, // Internal LAN disable 140 US1D, 1, // UHCI #1 disable 141 US2D, 1, // UHCI #2 disable 142 US3D, 1, // UHCI #3 disable 143 US4D, 1, // UHCI #4 disable 144 , 2, // Reserved 145 LPBD, 1, // LPC bridge disable 146 EHCD, 1, // EHCI disable 147 // FD Root Ports 148 RP1D, 1, // Root Port 1 disable 149 RP2D, 1, // Root Port 2 disable 150 RP3D, 1, // Root Port 3 disable 151 RP4D, 1, // Root Port 4 disable 152 RP5D, 1, // Root Port 5 disable 153 RP6D, 1 // Root Port 6 disable 154 } 155 156} 157 158// 0:1b.0 High Definition Audio (Azalia) 159#include <southbridge/intel/common/acpi/audio_ich.asl> 160 161// PCI Express Ports 162#include <southbridge/intel/common/acpi/pcie.asl> 163 164// USB 165#include "usb.asl" 166 167// PCI Bridge 168#include "pci.asl" 169 170// AC97 Audio and Modem 171#include "ac97.asl" 172 173// LPC Bridge 174#include "lpc.asl" 175 176// PATA 177#include "pata.asl" 178 179// SATA 180#include "sata.asl" 181 182// SMBus 183#include <southbridge/intel/common/acpi/smbus.asl> 184