1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOUTHBRIDGE_INTEL_I82801GX_CHIP_H 4 #define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H 5 6 #include <types.h> 7 8 enum sata_mode { 9 SATA_MODE_AHCI = 0, 10 SATA_MODE_IDE_LEGACY_COMBINED, 11 SATA_MODE_IDE_PLAIN, 12 }; 13 14 struct southbridge_intel_i82801gx_config { 15 /** 16 * Interrupt Routing configuration 17 * If bit7 is 1, the interrupt is disabled. 18 */ 19 uint8_t pirqa_routing; 20 uint8_t pirqb_routing; 21 uint8_t pirqc_routing; 22 uint8_t pirqd_routing; 23 uint8_t pirqe_routing; 24 uint8_t pirqf_routing; 25 uint8_t pirqg_routing; 26 uint8_t pirqh_routing; 27 28 /** 29 * GPI Routing configuration 30 * 31 * Only the lower two bits have a meaning: 32 * 00: No effect 33 * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) 34 * 10: SCI (if corresponding GPIO_EN bit is also set) 35 * 11: reserved 36 */ 37 uint8_t gpi0_routing; 38 uint8_t gpi1_routing; 39 uint8_t gpi2_routing; 40 uint8_t gpi3_routing; 41 uint8_t gpi4_routing; 42 uint8_t gpi5_routing; 43 uint8_t gpi6_routing; 44 uint8_t gpi7_routing; 45 uint8_t gpi8_routing; 46 uint8_t gpi9_routing; 47 uint8_t gpi10_routing; 48 uint8_t gpi11_routing; 49 uint8_t gpi12_routing; 50 uint8_t gpi13_routing; 51 uint8_t gpi14_routing; 52 uint8_t gpi15_routing; 53 54 uint32_t gpe0_en; 55 uint16_t alt_gp_smi_en; 56 57 /* IDE configuration */ 58 bool ide_enable_primary; 59 bool ide_enable_secondary; 60 enum sata_mode sata_mode; 61 uint32_t sata_ports_implemented; 62 63 /* Enable linear PCIe Root Port function numbers starting at zero */ 64 bool pcie_port_coalesce; 65 66 bool c4onc3_enable; 67 bool docking_supported; 68 bool p_cnt_throttling_supported; 69 int c3_latency; 70 71 /* Additional LPC IO decode ranges */ 72 uint32_t gen1_dec; 73 uint32_t gen2_dec; 74 uint32_t gen3_dec; 75 uint32_t gen4_dec; 76 }; 77 78 #endif /* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */ 79