1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H 4 #define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H 5 6 #include <stdbool.h> 7 #include <stdint.h> 8 9 enum { 10 THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3, 11 THTL_50_0 = 4, THTL_37_5 = 5, THTL_25_0 = 6, THTL_12_5 = 7 12 }; 13 14 struct southbridge_intel_i82801ix_config { 15 /** 16 * Interrupt Routing configuration 17 * If bit7 is 1, the interrupt is disabled. 18 */ 19 uint8_t pirqa_routing; 20 uint8_t pirqb_routing; 21 uint8_t pirqc_routing; 22 uint8_t pirqd_routing; 23 uint8_t pirqe_routing; 24 uint8_t pirqf_routing; 25 uint8_t pirqg_routing; 26 uint8_t pirqh_routing; 27 28 /** 29 * GPI Routing configuration 30 * 31 * Only the lower two bits have a meaning: 32 * 00: No effect 33 * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) 34 * 10: SCI (if corresponding GPIO_EN bit is also set) 35 * 11: reserved 36 */ 37 uint8_t gpi0_routing; 38 uint8_t gpi1_routing; 39 uint8_t gpi2_routing; 40 uint8_t gpi3_routing; 41 uint8_t gpi4_routing; 42 uint8_t gpi5_routing; 43 uint8_t gpi6_routing; 44 uint8_t gpi7_routing; 45 uint8_t gpi8_routing; 46 uint8_t gpi9_routing; 47 uint8_t gpi10_routing; 48 uint8_t gpi11_routing; 49 uint8_t gpi12_routing; 50 uint8_t gpi13_routing; 51 uint8_t gpi14_routing; 52 uint8_t gpi15_routing; 53 54 uint32_t gpe0_en; 55 uint16_t alt_gp_smi_en; 56 57 /* IDE configuration */ 58 uint8_t sata_port_map : 6; 59 bool sata_clock_request; 60 bool sata_traffic_monitor; 61 62 bool c4onc3_enable; 63 bool c5_enable; 64 bool c6_enable; 65 66 unsigned int throttle_duty : 3; 67 68 /* Bit mask to tell whether a PCIe slot is implemented as slot. */ 69 unsigned int pcie_slot_implemented : 6; 70 71 /* Power limits for PCIe ports. Values are in 10^(-scale) watts. */ 72 struct { 73 uint8_t value : 8; 74 uint8_t scale : 2; 75 } pcie_power_limits[6]; 76 77 bool pcie_hotplug_map[8]; 78 79 /* Additional LPC IO decode ranges */ 80 uint32_t gen1_dec; 81 uint32_t gen2_dec; 82 uint32_t gen3_dec; 83 uint32_t gen4_dec; 84 }; 85 86 #endif /* SOUTHBRIDGE_INTEL_I82801IX_CHIP_H */ 87