1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <cpu/intel/speedstep.h>
4 #include <console/console.h>
5 #include <device/device.h>
6 #include <device/pci.h>
7 #include <device/pci_ids.h>
8 #include <option.h>
9 #include <pc80/mc146818rtc.h>
10 #include <pc80/isa-dma.h>
11 #include <pc80/i8259.h>
12 #include <arch/io.h>
13 #include <device/pci_ops.h>
14 #include <arch/ioapic.h>
15 #include <acpi/acpi.h>
16 #include <cpu/x86/smm.h>
17 #include <acpi/acpigen.h>
18 #include "chip.h"
19 #include "i82801ix.h"
20 #include <southbridge/intel/common/pciehp.h>
21 #include <southbridge/intel/common/pmutil.h>
22 #include <southbridge/intel/common/acpi_pirq_gen.h>
23 #include <southbridge/intel/common/rcba_pirq.h>
24
25 #define NMI_OFF 0
26
27 typedef struct southbridge_intel_i82801ix_config config_t;
28
i82801ix_enable_apic(struct device * dev)29 static void i82801ix_enable_apic(struct device *dev)
30 {
31 /* Enable IOAPIC. Keep APIC Range Select at zero. */
32 RCBA8(0x31ff) = 0x03;
33 /* We have to read 0x31ff back if bit0 changed. */
34 RCBA8(0x31ff);
35
36 /* Lock maximum redirection entries (MRE), R/WO register. */
37 ioapic_lock_max_vectors(IO_APIC_ADDR);
38
39 register_new_ioapic_gsi0(IO_APIC_ADDR);
40 }
41
i82801ix_enable_serial_irqs(struct device * dev)42 static void i82801ix_enable_serial_irqs(struct device *dev)
43 {
44 /* Set packet length and toggle silent mode bit for one frame. */
45 pci_write_config8(dev, D31F0_SERIRQ_CNTL,
46 (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
47 }
48
49 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
50 * 0x00 - 0000 = Reserved
51 * 0x01 - 0001 = Reserved
52 * 0x02 - 0010 = Reserved
53 * 0x03 - 0011 = IRQ3
54 * 0x04 - 0100 = IRQ4
55 * 0x05 - 0101 = IRQ5
56 * 0x06 - 0110 = IRQ6
57 * 0x07 - 0111 = IRQ7
58 * 0x08 - 1000 = Reserved
59 * 0x09 - 1001 = IRQ9
60 * 0x0A - 1010 = IRQ10
61 * 0x0B - 1011 = IRQ11
62 * 0x0C - 1100 = IRQ12
63 * 0x0D - 1101 = Reserved
64 * 0x0E - 1110 = IRQ14
65 * 0x0F - 1111 = IRQ15
66 * PIRQ[n]_ROUT[7] - PIRQ Routing Control
67 * 0x80 - The PIRQ is not routed.
68 */
69
i82801ix_pirq_init(struct device * dev)70 static void i82801ix_pirq_init(struct device *dev)
71 {
72 struct device *irq_dev;
73 /* Get the chip configuration */
74 config_t *config = dev->chip_info;
75
76 pci_write_config8(dev, D31F0_PIRQA_ROUT, config->pirqa_routing);
77 pci_write_config8(dev, D31F0_PIRQB_ROUT, config->pirqb_routing);
78 pci_write_config8(dev, D31F0_PIRQC_ROUT, config->pirqc_routing);
79 pci_write_config8(dev, D31F0_PIRQD_ROUT, config->pirqd_routing);
80
81 pci_write_config8(dev, D31F0_PIRQE_ROUT, config->pirqe_routing);
82 pci_write_config8(dev, D31F0_PIRQF_ROUT, config->pirqf_routing);
83 pci_write_config8(dev, D31F0_PIRQG_ROUT, config->pirqg_routing);
84 pci_write_config8(dev, D31F0_PIRQH_ROUT, config->pirqh_routing);
85
86 /* Eric Biederman once said we should let the OS do this.
87 * I am not so sure anymore he was right.
88 */
89
90 for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
91 u8 int_pin = 0, int_line = 0;
92
93 if (!is_enabled_pci(irq_dev))
94 continue;
95
96 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
97
98 switch (int_pin) {
99 case 1: /* INTA# */ int_line = config->pirqa_routing; break;
100 case 2: /* INTB# */ int_line = config->pirqb_routing; break;
101 case 3: /* INTC# */ int_line = config->pirqc_routing; break;
102 case 4: /* INTD# */ int_line = config->pirqd_routing; break;
103 }
104
105 if (!int_line)
106 continue;
107
108 pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
109 }
110 }
111
i82801ix_gpi_routing(struct device * dev)112 static void i82801ix_gpi_routing(struct device *dev)
113 {
114 /* Get the chip configuration */
115 config_t *config = dev->chip_info;
116 u32 reg32 = 0;
117
118 /* An array would be much nicer here, or some
119 * other method of doing this.
120 */
121 reg32 |= (config->gpi0_routing & 0x03) << 0;
122 reg32 |= (config->gpi1_routing & 0x03) << 2;
123 reg32 |= (config->gpi2_routing & 0x03) << 4;
124 reg32 |= (config->gpi3_routing & 0x03) << 6;
125 reg32 |= (config->gpi4_routing & 0x03) << 8;
126 reg32 |= (config->gpi5_routing & 0x03) << 10;
127 reg32 |= (config->gpi6_routing & 0x03) << 12;
128 reg32 |= (config->gpi7_routing & 0x03) << 14;
129 reg32 |= (config->gpi8_routing & 0x03) << 16;
130 reg32 |= (config->gpi9_routing & 0x03) << 18;
131 reg32 |= (config->gpi10_routing & 0x03) << 20;
132 reg32 |= (config->gpi11_routing & 0x03) << 22;
133 reg32 |= (config->gpi12_routing & 0x03) << 24;
134 reg32 |= (config->gpi13_routing & 0x03) << 26;
135 reg32 |= (config->gpi14_routing & 0x03) << 28;
136 reg32 |= (config->gpi15_routing & 0x03) << 30;
137
138 pci_write_config32(dev, D31F0_GPIO_ROUT, reg32);
139 }
140
southbridge_support_c5(void)141 bool southbridge_support_c5(void)
142 {
143 struct device *lpc_dev = __pci_0_1f_0;
144 struct southbridge_intel_i82801ix_config *config = lpc_dev->chip_info;
145 return config->c5_enable;
146 }
147
southbridge_support_c6(void)148 bool southbridge_support_c6(void)
149 {
150 struct device *lpc_dev = __pci_0_1f_0;
151 struct southbridge_intel_i82801ix_config *config = lpc_dev->chip_info;
152 return config->c6_enable;
153 }
154
i82801ix_power_options(struct device * dev)155 static void i82801ix_power_options(struct device *dev)
156 {
157 u8 reg8;
158 u16 reg16, pmbase;
159 u32 reg32;
160 const char *state;
161 /* Get the chip configuration */
162 config_t *config = dev->chip_info;
163
164 /* BIOS must program... */
165 pci_or_config32(dev, 0xac, (1 << 30) | (3 << 8));
166
167 /* Which state do we want to goto after g3 (power restored)?
168 * 0 == S0 Full On
169 * 1 == S5 Soft Off
170 *
171 * If the option is not existent (Laptops), use MAINBOARD_POWER_ON.
172 */
173 const unsigned int pwr_on = get_uint_option("power_on_after_fail", MAINBOARD_POWER_ON);
174
175 reg8 = pci_read_config8(dev, D31F0_GEN_PMCON_3);
176 reg8 &= 0xfe;
177 switch (pwr_on) {
178 case MAINBOARD_POWER_OFF:
179 reg8 |= 1;
180 state = "off";
181 break;
182 case MAINBOARD_POWER_ON:
183 reg8 &= ~1;
184 state = "on";
185 break;
186 case MAINBOARD_POWER_KEEP:
187 reg8 &= ~1;
188 state = "state keep";
189 break;
190 default:
191 state = "undefined";
192 }
193
194 reg8 |= (3 << 4); /* avoid #S4 assertions */
195 reg8 &= ~(1 << 3); /* minimum assertion is 1 to 2 RTCCLK */
196
197 pci_write_config8(dev, D31F0_GEN_PMCON_3, reg8);
198 printk(BIOS_INFO, "Set power %s after power failure.\n", state);
199
200 /* Set up NMI on errors. */
201 reg8 = inb(0x61);
202 reg8 &= 0x0f; /* Higher Nibble must be 0 */
203 reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
204 // reg8 &= ~(1 << 2); /* PCI SERR# Enable */
205 reg8 |= (1 << 2); /* PCI SERR# Disable for now */
206 outb(reg8, 0x61);
207
208 reg8 = inb(0x74); /* Read from 0x74 as 0x70 is write only. */
209 const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF);
210 if (nmi_option) {
211 printk(BIOS_INFO, "NMI sources enabled.\n");
212 reg8 &= ~(1 << 7); /* Set NMI. */
213 } else {
214 printk(BIOS_INFO, "NMI sources disabled.\n");
215 reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
216 }
217 outb(reg8, 0x70);
218
219 /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
220 reg16 = pci_read_config16(dev, D31F0_GEN_PMCON_1);
221 reg16 &= ~(3 << 0); // SMI# rate 1 minute
222 reg16 |= (1 << 2); // CLKRUN_EN - Mobile/Ultra only
223 reg16 |= (1 << 3); // Speedstep Enable - Mobile/Ultra only
224 reg16 |= (1 << 5); // CPUSLP_EN Desktop only
225
226 if (config->c4onc3_enable)
227 reg16 |= (1 << 7);
228
229 // another laptop wants this?
230 // reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
231 reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
232 if (CONFIG(DEBUG_PERIODIC_SMI))
233 reg16 |= (3 << 0); // Periodic SMI every 8s
234 if (southbridge_support_c5())
235 reg16 |= (1 << 11); /* Enable C5, C6 and PMSYNC# */
236 pci_write_config16(dev, D31F0_GEN_PMCON_1, reg16);
237
238 /* Set exit timings for C5/C6. */
239 if (southbridge_support_c5()) {
240 reg8 = pci_read_config8(dev, D31F0_C5_EXIT_TIMING);
241 reg8 &= ~((7 << 3) | (7 << 0));
242 if (southbridge_support_c6())
243 reg8 |= (5 << 3) | (3 << 0); /* 38-44us PMSYNC# to STPCLK#,
244 95-102us DPRSTP# to STP_CPU# */
245 else
246 reg8 |= (0 << 3) | (1 << 0); /* 16-17us PMSYNC# to STPCLK#,
247 34-40us DPRSTP# to STP_CPU# */
248 pci_write_config8(dev, D31F0_C5_EXIT_TIMING, reg8);
249 }
250
251 // Set the board's GPI routing.
252 i82801ix_gpi_routing(dev);
253
254 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
255
256 outl(config->gpe0_en, pmbase + 0x28);
257 outw(config->alt_gp_smi_en, pmbase + 0x38);
258
259 /* Set up power management block and determine sleep mode */
260 reg16 = inw(pmbase + 0x00); /* PM1_STS */
261 outw(reg16, pmbase + 0x00); /* Clear status bits. At least bit11 (power
262 button override) must be cleared or SCI
263 will be constantly fired and OSPM must
264 not know about it (ACPI spec says to
265 ignore the bit). */
266
267 /* Set duty cycle for hardware throttling (defaults to 0x0: 50%). */
268 reg32 = inl(pmbase + 0x10);
269 reg32 &= ~(7 << 5);
270 reg32 |= (config->throttle_duty & 7) << 5;
271 outl(reg32, pmbase + 0x10);
272 }
273
i82801ix_configure_cstates(struct device * dev)274 static void i82801ix_configure_cstates(struct device *dev)
275 {
276 // Enable Popup & Popdown
277 pci_or_config8(dev, D31F0_CxSTATE_CNF, (1 << 4) | (1 << 3) | (1 << 2));
278
279 // Set Deeper Sleep configuration to recommended values
280 // Deeper Sleep to Stop CPU: 34-40us
281 // Deeper Sleep to Sleep: 15us
282 pci_update_config8(dev, D31F0_C4TIMING_CNT, ~0x0f, (2 << 2) | (2 << 0));
283
284 /* We could enable slow-C4 exit here, if someone needs it? */
285 }
286
i82801ix_rtc_init(struct device * dev)287 static void i82801ix_rtc_init(struct device *dev)
288 {
289 u8 reg8;
290 int rtc_failed;
291
292 reg8 = pci_read_config8(dev, D31F0_GEN_PMCON_3);
293 rtc_failed = reg8 & RTC_BATTERY_DEAD;
294 if (rtc_failed) {
295 reg8 &= ~RTC_BATTERY_DEAD;
296 pci_write_config8(dev, D31F0_GEN_PMCON_3, reg8);
297 }
298 printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
299
300 cmos_init(rtc_failed);
301 }
302
enable_hpet(void)303 static void enable_hpet(void)
304 {
305 u32 reg32;
306
307 /* Move HPET to default address 0xfed00000 and enable it */
308 reg32 = RCBA32(RCBA_HPTC);
309 reg32 |= (1 << 7); // HPET Address Enable
310 reg32 &= ~(3 << 0);
311 RCBA32(RCBA_HPTC) = reg32;
312 }
313
enable_clock_gating(void)314 static void enable_clock_gating(void)
315 {
316 u32 reg32;
317
318 /* Enable DMI dynamic clock gating. */
319 RCBA32(RCBA_DMIC) |= 3;
320
321 /* Enable Clock Gating for most devices. */
322 reg32 = RCBA32(RCBA_CG);
323 reg32 |= (1 << 31); /* LPC dynamic clock gating */
324 /* USB UHCI dynamic clock gating: */
325 reg32 |= (1 << 29) | (1 << 28);
326 /* SATA dynamic clock gating [0-3]: */
327 reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
328 reg32 |= (1 << 23); /* LAN static clock gating (if LAN disabled) */
329 reg32 |= (1 << 22); /* HD audio dynamic clock gating */
330 reg32 &= ~(1 << 21); /* No HD audio static clock gating */
331 reg32 &= ~(1 << 20); /* No USB EHCI static clock gating */
332 reg32 |= (1 << 19); /* USB EHCI dynamic clock gating */
333 /* More SATA dynamic clock gating [4-5]: */
334 reg32 |= (1 << 18) | (1 << 17);
335 reg32 |= (1 << 16); /* PCI dynamic clock gating */
336 /* PCIe, DMI dynamic clock gating: */
337 reg32 |= (1 << 4) | (1 << 3) | (1 << 2) | (1 << 1);
338 reg32 |= (1 << 0); /* PCIe root port static clock gating */
339 RCBA32(RCBA_CG) = reg32;
340
341 /* Enable SPI dynamic clock gating. */
342 RCBA32(0x38c0) |= 7;
343 }
344
i82801ix_set_acpi_mode(struct device * dev)345 static void i82801ix_set_acpi_mode(struct device *dev)
346 {
347 if (!acpi_is_wakeup_s3()) {
348 apm_control(APM_CNT_ACPI_DISABLE);
349 } else {
350 apm_control(APM_CNT_ACPI_ENABLE);
351 }
352 }
353
lpc_init(struct device * dev)354 static void lpc_init(struct device *dev)
355 {
356 printk(BIOS_DEBUG, "i82801ix: %s\n", __func__);
357
358 /* IO APIC initialization. */
359 i82801ix_enable_apic(dev);
360
361 i82801ix_enable_serial_irqs(dev);
362
363 /* Setup the PIRQ. */
364 i82801ix_pirq_init(dev);
365
366 /* Setup power options. */
367 i82801ix_power_options(dev);
368
369 /* Configure Cx state registers */
370 if (LPC_IS_MOBILE(dev))
371 i82801ix_configure_cstates(dev);
372
373 /* Initialize the real time clock. */
374 i82801ix_rtc_init(dev);
375
376 /* Initialize ISA DMA. */
377 isa_dma_init();
378
379 /* Initialize the High Precision Event Timers, if present. */
380 enable_hpet();
381
382 /* Initialize Clock Gating */
383 enable_clock_gating();
384
385 setup_i8259();
386
387 /* The OS should do this? */
388 /* Interrupt 9 should be level triggered (SCI) */
389 i8259_configure_irq_trigger(9, 1);
390
391 i82801ix_set_acpi_mode(dev);
392 }
393
i82801ix_lpc_read_resources(struct device * dev)394 static void i82801ix_lpc_read_resources(struct device *dev)
395 {
396 /*
397 * I/O Resources
398 *
399 * 0x0000 - 0x000f....ISA DMA
400 * 0x0010 - 0x001f....ISA DMA aliases
401 * 0x0020 ~ 0x003d....PIC
402 * 0x002e - 0x002f....Maybe Super I/O
403 * 0x0040 - 0x0043....Timer
404 * 0x004e - 0x004f....Maybe Super I/O
405 * 0x0050 - 0x0053....Timer aliases
406 * 0x0061.............NMI_SC
407 * 0x0070.............NMI_EN (readable in alternative access mode)
408 * 0x0070 - 0x0077....RTC
409 * 0x0080 - 0x008f....ISA DMA
410 * 0x0090 ~ 0x009f....ISA DMA aliases
411 * 0x0092.............Fast A20 and Init
412 * 0x00a0 ~ 0x00bd....PIC
413 * 0x00b2 - 0x00b3....APM
414 * 0x00c0 ~ 0x00de....ISA DMA
415 * 0x00c1 ~ 0x00df....ISA DMA aliases
416 * 0x00f0.............Coprocessor Error
417 * (0x0400-0x041f)....SMBus (CONFIG_FIXED_SMBUS_IO_BASE, during raminit)
418 * 0x04d0 - 0x04d1....PIC
419 * 0x0500 - 0x057f....PM (DEFAULT_PMBASE)
420 * 0x0580 - 0x05bf....SB GPIO (DEFAULT_GPIOBASE)
421 * 0x05c0 - 0x05ff....SB GPIO cont. (mobile only)
422 * 0x0cf8 - 0x0cff....PCI
423 * 0x0cf9.............Reset Control
424 */
425
426 struct resource *res;
427
428 /* Get the normal PCI resources of this device. */
429 pci_dev_read_resources(dev);
430
431 /* Add an extra subtractive resource for both memory and I/O. */
432 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
433 res->base = 0;
434 res->size = 0x1000;
435 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
436 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
437
438 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
439 res->base = 0xff800000;
440 res->size = 0x00800000; /* 8 MB for flash */
441 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
442 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
443
444 res = new_resource(dev, 3); /* IOAPIC */
445 res->base = IO_APIC_ADDR;
446 res->size = 0x00001000;
447 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
448 }
449
lpc_acpi_name(const struct device * dev)450 static const char *lpc_acpi_name(const struct device *dev)
451 {
452 return "LPCB";
453 }
454
southbridge_fill_ssdt(const struct device * device)455 static void southbridge_fill_ssdt(const struct device *device)
456 {
457 struct device *dev = pcidev_on_root(0x1f, 0);
458 config_t *chip = dev->chip_info;
459
460 intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
461 intel_acpi_gen_def_acpi_pirq(device);
462 }
463
464 static struct device_operations device_ops = {
465 .read_resources = i82801ix_lpc_read_resources,
466 .set_resources = pci_dev_set_resources,
467 .enable_resources = pci_dev_enable_resources,
468 .write_acpi_tables = acpi_write_hpet,
469 .acpi_fill_ssdt = southbridge_fill_ssdt,
470 .acpi_name = lpc_acpi_name,
471 .init = lpc_init,
472 .scan_bus = scan_static_bus,
473 .ops_pci = &pci_dev_ops_pci,
474 };
475
476 static const unsigned short pci_device_ids[] = {
477 PCI_DID_INTEL_82801IH_LPC, /* ICH9DH */
478 PCI_DID_INTEL_82801IO_LPC, /* ICH9DO */
479 PCI_DID_INTEL_82801IR_LPC, /* ICH9R */
480 PCI_DID_INTEL_82801IEM_LPC, /* ICH9M-E */
481 PCI_DID_INTEL_82801IB_LPC, /* ICH9 */
482 PCI_DID_INTEL_82801IBM_LPC, /* ICH9M */
483 0
484 };
485
486 static const struct pci_driver ich9_lpc __pci_driver = {
487 .ops = &device_ops,
488 .vendor = PCI_VID_INTEL,
489 .devices = pci_device_ids,
490 };
491