1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <arch/ioapic.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include <device/pci_ops.h>
8 #include <assert.h>
9 #include <types.h>
10 #include "82870.h"
11
p64h2_ioapic_enable(struct device * dev)12 static void p64h2_ioapic_enable(struct device *dev)
13 {
14 /* We have to enable MEM and Bus Master for IOAPIC */
15 uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
16
17 pci_write_config16(dev, PCI_COMMAND, command);
18 }
19
20 /**
21 * Configure one of the IOAPICs in a P64H2.
22 *
23 * Note that a PCI bus scan will detect both IOAPICs, so this function
24 * will be called twice for each P64H2 in the system.
25 *
26 * @param dev PCI bus/device/function of P64H2 IOAPIC.
27 * NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0.
28 */
p64h2_ioapic_init(struct device * dev)29 static void p64h2_ioapic_init(struct device *dev)
30 {
31 uintptr_t memoryBase;
32
33 // Read the MBAR address for setting up the IOAPIC in memory space
34 // NOTE: this address was assigned during enumeration of the bus
35
36 memoryBase = (uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
37
38 register_new_ioapic(memoryBase);
39
40 // Use Processor System Bus to deliver interrupts
41 ioapic_set_boot_config(memoryBase, true);
42 }
43
44 static struct device_operations ioapic_ops = {
45 .read_resources = pci_dev_read_resources,
46 .set_resources = pci_dev_set_resources,
47 .enable_resources = pci_dev_enable_resources,
48 .init = p64h2_ioapic_init,
49 .enable = p64h2_ioapic_enable,
50 };
51
52 static const struct pci_driver ioapic_driver __pci_driver = {
53 .ops = &ioapic_ops,
54 .vendor = PCI_VID_INTEL,
55 .device = PCI_DID_INTEL_82870_1E0,
56
57 };
58