1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include <device/pci_ops.h>
8 #include <device/mmio.h>
9 #include <delay.h>
10 #include <device/azalia_device.h>
11 #include "pch.h"
12
codec_detect(u8 * base)13 static int codec_detect(u8 *base)
14 {
15 u8 reg8;
16
17 if (azalia_exit_reset(base) < 0)
18 goto no_codec;
19
20 /* Write back the value once reset bit is set. */
21 write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG));
22
23 /* Read in Codec location (BAR + 0xe)[2..0] */
24 reg8 = read8(base + HDA_STATESTS_REG);
25 reg8 &= 0x0f;
26 if (!reg8)
27 goto no_codec;
28
29 return reg8;
30
31 no_codec:
32 /* Codec not found, put HDA back in reset */
33 azalia_enter_reset(base);
34 printk(BIOS_DEBUG, "Azalia: No codec!\n");
35 return 0;
36 }
37
azalia_init(struct device * dev)38 static void azalia_init(struct device *dev)
39 {
40 u8 *base;
41 struct resource *res;
42 u32 codec_mask;
43 u32 reg32;
44
45 /* Find base address */
46 res = probe_resource(dev, PCI_BASE_ADDRESS_0);
47 if (!res)
48 return;
49
50 // NOTE this will break as soon as the Azalia gets a bar above 4G.
51 // Is there anything we can do about it?
52 base = res2mmio(res, 0, 0);
53 printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
54
55 if (RCBA32(0x2030) & (1 << 31)) {
56 reg32 = pci_read_config32(dev, 0x120);
57 reg32 &= 0xf8ffff01;
58 reg32 |= (1 << 24); // 2 << 24 for server
59 reg32 |= RCBA32(0x2030) & 0xfe;
60 pci_write_config32(dev, 0x120, reg32);
61
62 pci_or_config16(dev, 0x78, 1 << 11);
63 } else
64 printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n");
65
66 pci_and_config32(dev, 0x114, ~0xfe);
67
68 // Set VCi enable bit
69 pci_or_config32(dev, 0x120, 1 << 31);
70
71 // Enable HDMI codec:
72 pci_or_config32(dev, 0xc4, 1 << 1);
73
74 pci_or_config8(dev, 0x43, 1 << 6);
75
76 pci_and_config32(dev, 0xd0, ~(1 << 31));
77
78 /* Set Bus Master */
79 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
80
81 pci_write_config8(dev, 0x3c, 0x0a); // unused?
82
83 /* Codec Initialization Programming Sequence */
84
85 /* Take controller out of reset */
86 reg32 = read32(base + HDA_GCTL_REG);
87 reg32 |= HDA_GCTL_CRST;
88 write32(base + HDA_GCTL_REG, reg32);
89 /* Wait 1ms */
90 udelay(1000);
91
92 // Select Azalia mode. This needs to be controlled via devicetree.cb
93 pci_or_config8(dev, 0x40, 1); // Audio Control
94
95 // Docking not supported
96 pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status
97
98 codec_mask = codec_detect(base);
99
100 if (codec_mask) {
101 printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
102 azalia_codecs_init(base, codec_mask);
103 }
104
105 /* Enable dynamic clock gating */
106 pci_update_config8(dev, 0x43, ~0x07, (1 << 2) | (1 << 0));
107 }
108
109 static struct device_operations azalia_ops = {
110 .read_resources = pci_dev_read_resources,
111 .set_resources = pci_dev_set_resources,
112 .enable_resources = pci_dev_enable_resources,
113 .init = azalia_init,
114 .ops_pci = &pci_dev_ops_pci,
115 };
116
117 static const unsigned short pci_device_ids[] = {
118 0x1c20,
119 0x1e20,
120 PCI_DID_INTEL_IBEXPEAK_AUDIO,
121 0
122 };
123
124 static const struct pci_driver pch_azalia __pci_driver = {
125 .ops = &azalia_ops,
126 .vendor = PCI_VID_INTEL,
127 .devices = pci_device_ids,
128 };
129